Difference between revisions of "PM Registers"
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Registers tend to be controlled on a bit level, so for the sanity purposes, they will be broken down to this level. At any point they are shown spanning multiple columns, that indicates that it is a multi-bit value and should be treated as if they were a number. | Registers tend to be controlled on a bit level, so for the sanity purposes, they will be broken down to this level. At any point they are shown spanning multiple columns, that indicates that it is a multi-bit value and should be treated as if they were a number. | ||
− | The bits themselves come in four flavors: Read-only, Write-Only, Read-Write, and S-R Strobe. Write-Only registers typically return a zero value, and are generally only used for things such as resetting timers. S-R Strobes are used for clearing interrupt events | + | The bits themselves come in four flavors: Read-only, Write-Only, Read-Write, and S-R Strobe. Write-Only registers typically return a zero value, and are generally only used for things such as resetting timers. S-R Strobes are used for clearing interrupt events, writting a logical '1' to any bit that is set will result in a bit being cleared, where as '0' leaves them unchanged. Unused bits always return '0'. |
Any register not included on this list reads as [[Open-Bus]] and will be excluded unless a function has otherwise been determined. | Any register not included on this list reads as [[Open-Bus]] and will be excluded unless a function has otherwise been determined. | ||
Line 20: | Line 20: | ||
| style="background-color:#FFFF00;"| Write Only | | style="background-color:#FFFF00;"| Write Only | ||
| style="background-color:#FFCC00;"| S-R Strobe | | style="background-color:#FFCC00;"| S-R Strobe | ||
+ | | style="background-color:#00FFC0;"| Read/Write (BIOS, Software only) | ||
+ | | style="background-color:#C0FF00;"| Unknown (Read/Write) | ||
+ | | style="background-color:#C0FFC0;"| Unknown (Weird) | ||
+ | | style="background-color:#C0C0C0;"| Unknown (Unused) | ||
|} | |} | ||
+ | |||
{| border="1" style="text-align:center;" | {| border="1" style="text-align:center;" | ||
+ | |+ '''Registers ($2000 to $20FF)''' | ||
! Address | ! Address | ||
! Register | ! Register | ||
! Const Name | ! Const Name | ||
− | ! 7 | + | ! < Bit 7 > |
− | ! 6 | + | ! < Bit 6 > |
− | ! 5 | + | ! < Bit 5 > |
− | ! 4 | + | ! < Bit 4 > |
− | ! 3 | + | ! < Bit 3 > |
− | ! 2 | + | ! < Bit 2 > |
− | ! 1 | + | ! < Bit 1 > |
− | ! 0 | + | ! < Bit 0 > |
|- | |- | ||
| $00 | | $00 | ||
| System Control 1 | | System Control 1 | ||
− | | | + | | SYS_CTRL1 |
− | | colspan="6" style="background-color:# | + | | colspan="6" style="background-color:#00FFC0;"| Startup Contrast |
− | | style="background-color:#80FF80;"| | + | | style="background-color:#80FF80;"| Cartridge I/O<br/>Enable |
− | | style="background-color:#80FF80;"| | + | | style="background-color:#80FF80;"| LCD I/O<br/>Enable |
|- | |- | ||
| $01 | | $01 | ||
+ | | System Control 2 | ||
+ | | SYS_CTRL2 | ||
+ | | style="background-color:#00FFC0;" | Ram vector | ||
+ | | style="background-color:#00FFC0;" | Int abort | ||
+ | | style="background-color:#00FFC0;" | Enable cart interrupts | ||
+ | | style="background-color:#00FFC0;" | Power on reset | ||
+ | | colspan="4" style="background-color:#00FFC0;" | Cart type | ||
|- | |- | ||
| $02 | | $02 | ||
+ | | System Control 3 | ||
+ | | SYS_CTRL3 | ||
+ | | style="background-color:#00FFC0;" | Cart power state | ||
+ | | style="background-color:#00FFC0;" | Cart power required | ||
+ | | style="background-color:#00FFC0;" | Suspend mode | ||
+ | | colspan="3" style="background-color:#00FFC0;" | ??? | ||
+ | | style="background-color:#00FFC0;" | RTC Timer valid | ||
+ | | style="background-color:#00FFC0;" | ??? | ||
|- | |- | ||
| $08 | | $08 | ||
− | | Second Counter Control | + | | [[PM Second Counter|Second Counter Control]] |
| SEC_CTRL | | SEC_CTRL | ||
| colspan="6" style="border:none;background-color:#808080;"| | | colspan="6" style="border:none;background-color:#808080;"| | ||
Line 54: | Line 75: | ||
|- | |- | ||
| $09 | | $09 | ||
− | | Second Counter | + | | [[PM Second Counter|Second Counter Low]] |
| SEC_CNT_LO | | SEC_CNT_LO | ||
| colspan="8" style="background-color:#00FFFF;"| Counter | | colspan="8" style="background-color:#00FFFF;"| Counter | ||
|- | |- | ||
| $0A | | $0A | ||
− | | Second Counter | + | | [[PM Second Counter|Second Counter Middle]] |
− | | | + | | SEC_CNT_MID |
| colspan="8" style="background-color:#00FFFF;"| Counter | | colspan="8" style="background-color:#00FFFF;"| Counter | ||
|- | |- | ||
| $0B | | $0B | ||
− | | Second Counter | + | | [[PM Second Counter|Second Counter High]] |
| SEC_CNT_HI | | SEC_CNT_HI | ||
| colspan="8" style="background-color:#00FFFF;"| Counter | | colspan="8" style="background-color:#00FFFF;"| Counter | ||
Line 73: | Line 94: | ||
| colspan="2" style="border:none;background-color:#808080;"| | | colspan="2" style="border:none;background-color:#808080;"| | ||
| style="background-color:#00FFFF;" | Low Battery | | style="background-color:#00FFFF;" | Low Battery | ||
− | | colspan=" | + | | style="background-color:#80FF80;" | Battery ADC control |
+ | | colspan="4" style="background-color:#80FF80;"| Battery ADC threshold value | ||
|- | |- | ||
| $18 | | $18 | ||
− | | Timer 1 Prescalars | + | | [[Timers|Timer 1 Prescalars]] |
− | | | + | | TMR1_SCALE |
| style="background-color:#80FF80;"| Enable Hi | | style="background-color:#80FF80;"| Enable Hi | ||
| colspan="3" style="background-color:#80FF80;"| Hi Scalar | | colspan="3" style="background-color:#80FF80;"| Hi Scalar | ||
− | | style="background-color:#80FF80;"| Enable | + | | style="background-color:#80FF80;"| Enable Lo |
− | | colspan="3" style="background-color:#80FF80;"| | + | | colspan="3" style="background-color:#80FF80;"| Lo Scalar |
|- | |- | ||
| $19 | | $19 | ||
− | | | + | | [[Timers|Timers Osc. Enable<br />Timer 1 Osc. Select]] |
− | | | + | | TMR1_ENA_OSC<br />TMR1_OSC |
| colspan="2" style="border:none;background-color:#808080;"| | | colspan="2" style="border:none;background-color:#808080;"| | ||
− | | style="background-color:#80FF80;"| Enable | + | | style="background-color:#80FF80;"| Enable Osc. 1 |
− | | style="background-color:#80FF80;"| Enable | + | | style="background-color:#80FF80;"| Enable Osc. 2 |
| colspan="2" style="border:none;background-color:#808080;"| | | colspan="2" style="border:none;background-color:#808080;"| | ||
− | | style="background-color:#80FF80;"| | + | | style="background-color:#80FF80;"| 2nd Osc. (Hi) |
− | | style="background-color:#80FF80;"| | + | | style="background-color:#80FF80;"| 2nd Osc. (Lo) |
|- | |- | ||
| $1A | | $1A | ||
− | | Timer 2 Prescalars | + | | [[Timers|Timer 2 Prescalars]] |
− | | | + | | TMR2_SCALE |
| style="background-color:#80FF80;"| Enable Hi | | style="background-color:#80FF80;"| Enable Hi | ||
| colspan="3" style="background-color:#80FF80;"| Hi Scalar | | colspan="3" style="background-color:#80FF80;"| Hi Scalar | ||
− | | style="background-color:#80FF80;"| Enable | + | | style="background-color:#80FF80;"| Enable Lo |
− | | colspan="3" style="background-color:#80FF80;"| | + | | colspan="3" style="background-color:#80FF80;"| Lo Scalar |
|- | |- | ||
| $1B | | $1B | ||
− | | Timer 2 | + | | [[Timers|Timer 2 Osc. Select]] |
− | | | + | | TMR2_OSC |
| colspan="6" style="border:none;background-color:#808080;"| | | colspan="6" style="border:none;background-color:#808080;"| | ||
− | | style="background-color:#80FF80;"| | + | | style="background-color:#80FF80;"| 2nd Osc. (Hi) |
− | | style="background-color:#80FF80;"| | + | | style="background-color:#80FF80;"| 2nd Osc. (Lo) |
|- | |- | ||
| $1C | | $1C | ||
− | | Timer 3 Prescalars | + | | [[Timers|Timer 3 Prescalars]] |
− | | | + | | TMR3_SCALE |
| style="background-color:#80FF80;"| Enable Hi | | style="background-color:#80FF80;"| Enable Hi | ||
| colspan="3" style="background-color:#80FF80;"| Hi Scalar | | colspan="3" style="background-color:#80FF80;"| Hi Scalar | ||
− | | style="background-color:#80FF80;"| Enable | + | | style="background-color:#80FF80;"| Enable Lo |
− | | colspan="3" style="background-color:#80FF80;"| | + | | colspan="3" style="background-color:#80FF80;"| Lo Scalar |
|- | |- | ||
| $1D | | $1D | ||
− | | Timer 3 | + | | [[Timers|Timer 3 Osc. Select]] |
− | | | + | | TMR3_OSC |
| colspan="6" style="border:none;background-color:#808080;"| | | colspan="6" style="border:none;background-color:#808080;"| | ||
− | | style="background-color:#80FF80;"| | + | | style="background-color:#80FF80;"| 2nd Osc. (Hi) |
− | | style="background-color:#80FF80;"| | + | | style="background-color:#80FF80;"| 2nd Osc. (Lo) |
|- | |- | ||
| $20 | | $20 | ||
| [[PM_IRQs|IRQ Priority 1]] | | [[PM_IRQs|IRQ Priority 1]] | ||
− | | | + | | IRQ_PRI1 |
| colspan="2" style="background-color:#80FF80;"| IRQ $03 ~ $04 | | colspan="2" style="background-color:#80FF80;"| IRQ $03 ~ $04 | ||
| colspan="2" style="background-color:#80FF80;"| IRQ $05 ~ $06 | | colspan="2" style="background-color:#80FF80;"| IRQ $05 ~ $06 | ||
Line 133: | Line 155: | ||
| $21 | | $21 | ||
| [[PM_IRQs|IRQ Priority 2]] | | [[PM_IRQs|IRQ Priority 2]] | ||
− | | | + | | IRQ_PRI2 |
| colspan="2" style="background-color:#80FF80;"| IRQ $0B ~ $0E | | colspan="2" style="background-color:#80FF80;"| IRQ $0B ~ $0E | ||
| colspan="2" style="background-color:#80FF80;"| IRQ $13 ~ $14 | | colspan="2" style="background-color:#80FF80;"| IRQ $13 ~ $14 | ||
| colspan="2" style="background-color:#80FF80;"| IRQ $15 ~ $1C | | colspan="2" style="background-color:#80FF80;"| IRQ $15 ~ $1C | ||
− | | colspan="2" style="background-color:#80FF80;"| IRQ ?? ($1D ~ $1F?) | + | | colspan="2" style="background-color:#80FF80;"| IRQ ??? ($1D ~ $1F?) |
|- | |- | ||
| $22 | | $22 | ||
| [[PM_IRQs|IRQ Priority 3]] | | [[PM_IRQs|IRQ Priority 3]] | ||
− | | | + | | IRQ_PRI3 |
| colspan="6" style="border:none;background-color:#808080;"| | | colspan="6" style="border:none;background-color:#808080;"| | ||
| colspan="2" style="background-color:#80FF80;"| IRQ $0F~$10 | | colspan="2" style="background-color:#80FF80;"| IRQ $0F~$10 | ||
Line 147: | Line 169: | ||
| $23 | | $23 | ||
| [[PM_IRQs|IRQ Enable 1]] | | [[PM_IRQs|IRQ Enable 1]] | ||
− | | | + | | IRQ_ENA1 |
| style="background-color:#80FF80;"| IRQ $03 | | style="background-color:#80FF80;"| IRQ $03 | ||
| style="background-color:#80FF80;"| IRQ $04 | | style="background-color:#80FF80;"| IRQ $04 | ||
Line 159: | Line 181: | ||
| $24 | | $24 | ||
| [[PM_IRQs|IRQ Enable 2]] | | [[PM_IRQs|IRQ Enable 2]] | ||
− | | | + | | IRQ_ENA2 |
| colspan="2" style="border:none;background-color:#808080;"| | | colspan="2" style="border:none;background-color:#808080;"| | ||
| style="background-color:#80FF80;"| IRQ $0B | | style="background-color:#80FF80;"| IRQ $0B | ||
Line 170: | Line 192: | ||
| $25 | | $25 | ||
| [[PM_IRQs|IRQ Enable 3]] | | [[PM_IRQs|IRQ Enable 3]] | ||
− | | | + | | IRQ_ENA3 |
| style="background-color:#80FF80;"| IRQ $15 | | style="background-color:#80FF80;"| IRQ $15 | ||
| style="background-color:#80FF80;"| IRQ $16 | | style="background-color:#80FF80;"| IRQ $16 | ||
Line 182: | Line 204: | ||
| $26 | | $26 | ||
| [[PM_IRQs|IRQ Enable 4]] | | [[PM_IRQs|IRQ Enable 4]] | ||
− | | | + | | IRQ_ENA4 |
| style="background-color:#80FF80;"| IRQ $0F | | style="background-color:#80FF80;"| IRQ $0F | ||
| style="background-color:#80FF80;"| IRQ $10 | | style="background-color:#80FF80;"| IRQ $10 | ||
− | | style="background-color:#80FF80;"| IRQ ?? | + | | style="background-color:#80FF80;"| IRQ ??? |
− | | style="background-color:#80FF80;"| IRQ ?? | + | | style="background-color:#80FF80;"| IRQ ??? |
| style="border:none;background-color:#808080;"| | | style="border:none;background-color:#808080;"| | ||
| style="background-color:#80FF80;"| IRQ $1D | | style="background-color:#80FF80;"| IRQ $1D | ||
Line 194: | Line 216: | ||
| $27 | | $27 | ||
| [[PM_IRQs|IRQ Active 1]] | | [[PM_IRQs|IRQ Active 1]] | ||
− | | | + | | IRQ_ACT1 |
| style="background-color:#FFCC00;"| IRQ $03 | | style="background-color:#FFCC00;"| IRQ $03 | ||
| style="background-color:#FFCC00;"| IRQ $04 | | style="background-color:#FFCC00;"| IRQ $04 | ||
Line 206: | Line 228: | ||
| $28 | | $28 | ||
| [[PM_IRQs|IRQ Active 2]] | | [[PM_IRQs|IRQ Active 2]] | ||
− | | | + | | IRQ_ACT2 |
| colspan="2" style="border:none;background-color:#808080;"| | | colspan="2" style="border:none;background-color:#808080;"| | ||
| style="background-color:#FFCC00;"| IRQ $0B | | style="background-color:#FFCC00;"| IRQ $0B | ||
Line 217: | Line 239: | ||
| $29 | | $29 | ||
| [[PM_IRQs|IRQ Active 3]] | | [[PM_IRQs|IRQ Active 3]] | ||
− | | | + | | IRQ_ACT3 |
| style="background-color:#FFCC00;"| IRQ $15 | | style="background-color:#FFCC00;"| IRQ $15 | ||
| style="background-color:#FFCC00;"| IRQ $16 | | style="background-color:#FFCC00;"| IRQ $16 | ||
Line 229: | Line 251: | ||
| $2A | | $2A | ||
| [[PM_IRQs|IRQ Active 4]] | | [[PM_IRQs|IRQ Active 4]] | ||
− | | | + | | IRQ_ACT4 |
| style="background-color:#FFCC00;"| IRQ $0F | | style="background-color:#FFCC00;"| IRQ $0F | ||
| style="background-color:#FFCC00;"| IRQ $10 | | style="background-color:#FFCC00;"| IRQ $10 | ||
− | | style="background-color:#FFCC00;"| IRQ ?? | + | | style="background-color:#FFCC00;"| IRQ ??? |
− | | style="background-color:#FFCC00;"| IRQ ?? | + | | style="background-color:#FFCC00;"| IRQ ??? |
| style="border:none;background-color:#808080;"| | | style="border:none;background-color:#808080;"| | ||
| style="background-color:#FFCC00;"| IRQ $1D | | style="background-color:#FFCC00;"| IRQ $1D | ||
Line 240: | Line 262: | ||
|- | |- | ||
| $30 | | $30 | ||
− | | Timer 1 Control (Lo) | + | | [[Timers|Timer 1 Control (Lo)]] |
− | | | + | | TMR1_CTRL_L |
| style="background-color:#80FF80;"| 16-bit Mode | | style="background-color:#80FF80;"| 16-bit Mode | ||
| colspan="3" style="border:none;background-color:#808080;"| | | colspan="3" style="border:none;background-color:#808080;"| | ||
Line 250: | Line 272: | ||
|- | |- | ||
| $31 | | $31 | ||
− | | Timer 1 Control (Hi) | + | | [[Timers|Timer 1 Control (Hi)]] |
− | | | + | | TMR1_CTRL_H |
| colspan="4" style="border:none;background-color:#808080;"| | | colspan="4" style="border:none;background-color:#808080;"| | ||
| style="background-color:#80FF80;"| ??? | | style="background-color:#80FF80;"| ??? | ||
Line 259: | Line 281: | ||
|- | |- | ||
| $32 | | $32 | ||
− | | Timer 1 Preset (Lo) | + | | [[Timers|Timer 1 Preset (Lo)]] |
− | | | + | | TMR1_PRE_L |
| colspan="8" style="background-color:#80FF80;"| Preset | | colspan="8" style="background-color:#80FF80;"| Preset | ||
|- | |- | ||
| $33 | | $33 | ||
− | | Timer 1 Preset (Hi) | + | | [[Timers|Timer 1 Preset (Hi)]] |
− | | | + | | TMR1_PRE_H |
| colspan="8" style="background-color:#80FF80;"| Preset | | colspan="8" style="background-color:#80FF80;"| Preset | ||
|- | |- | ||
| $34 | | $34 | ||
− | | Timer 1 Pivot (Lo) | + | | [[Timers|Timer 1 Pivot (Lo)]] |
− | | | + | | TMR1_PVT_L |
| colspan="8" style="background-color:#80FF80;"| Pivot | | colspan="8" style="background-color:#80FF80;"| Pivot | ||
|- | |- | ||
| $35 | | $35 | ||
− | | Timer 1 Pivot (Hi) | + | | [[Timers|Timer 1 Pivot (Hi)]] |
− | | | + | | TMR1_PVT_H |
| colspan="8" style="background-color:#80FF80;"| Pivot | | colspan="8" style="background-color:#80FF80;"| Pivot | ||
|- | |- | ||
| $36 | | $36 | ||
− | | Timer 1 Count (Lo) | + | | [[Timers|Timer 1 Count (Lo)]] |
− | | | + | | TMR1_CNT_L |
| colspan="8" style="background-color:#00FFFF;"| Count | | colspan="8" style="background-color:#00FFFF;"| Count | ||
|- | |- | ||
| $37 | | $37 | ||
− | | Timer 1 Count (Hi) | + | | [[Timers|Timer 1 Count (Hi)]] |
− | | | + | | TMR1_CNT_H |
| colspan="8" style="background-color:#00FFFF;"| Count | | colspan="8" style="background-color:#00FFFF;"| Count | ||
|- | |- | ||
| $38 | | $38 | ||
− | | Timer 2 Control (Lo) | + | | [[Timers|Timer 2 Control (Lo)]] |
− | | | + | | TMR2_CTRL_L |
| style="background-color:#80FF80;"| 16-bit Mode | | style="background-color:#80FF80;"| 16-bit Mode | ||
| colspan="3" style="border:none;background-color:#808080;"| | | colspan="3" style="border:none;background-color:#808080;"| | ||
Line 299: | Line 321: | ||
|- | |- | ||
| $39 | | $39 | ||
− | | Timer 2 Control ( | + | | [[Timers|Timer 2 Control (Hi)]] |
− | | | + | | TMR2_CTRL_H |
| colspan="4" style="border:none;background-color:#808080;"| | | colspan="4" style="border:none;background-color:#808080;"| | ||
| style="background-color:#80FF80;"| ??? | | style="background-color:#80FF80;"| ??? | ||
| style="background-color:#80FF80;"| Enable | | style="background-color:#80FF80;"| Enable | ||
− | |style="background-color:#FFFF00;"| Reset | + | | style="background-color:#FFFF00;"| Reset |
| style="background-color:#80FF80;"| ??? | | style="background-color:#80FF80;"| ??? | ||
|- | |- | ||
| $3A | | $3A | ||
− | | Timer 2 Preset (Lo) | + | | [[Timers|Timer 2 Preset (Lo)]] |
− | | | + | | TMR2_PRE_L |
| colspan="8" style="background-color:#80FF80;"| Preset | | colspan="8" style="background-color:#80FF80;"| Preset | ||
|- | |- | ||
| $3B | | $3B | ||
− | | Timer 2 Preset (Hi) | + | | [[Timers|Timer 2 Preset (Hi)]] |
− | | | + | | TMR2_PRE_H |
| colspan="8" style="background-color:#80FF80;"| Preset | | colspan="8" style="background-color:#80FF80;"| Preset | ||
|- | |- | ||
| $3C | | $3C | ||
− | | Timer 2 Pivot (Lo) | + | | [[Timers|Timer 2 Pivot (Lo)]] |
− | | | + | | TMR2_PVT_L |
| colspan="8" style="background-color:#80FF80;"| Pivot | | colspan="8" style="background-color:#80FF80;"| Pivot | ||
|- | |- | ||
| $3D | | $3D | ||
− | | Timer 2 Pivot (Hi) | + | | [[Timers|Timer 2 Pivot (Hi)]] |
− | | | + | | TMR2_PVT_H |
| colspan="8" style="background-color:#80FF80;"| Pivot | | colspan="8" style="background-color:#80FF80;"| Pivot | ||
|- | |- | ||
| $3E | | $3E | ||
− | | Timer 2 Count (Lo) | + | | [[Timers|Timer 2 Count (Lo)]] |
− | | | + | | TMR2_CNT_L |
| colspan="8" style="background-color:#00FFFF;"| Count | | colspan="8" style="background-color:#00FFFF;"| Count | ||
|- | |- | ||
| $3F | | $3F | ||
− | | Timer 2 Count (Hi) | + | | [[Timers|Timer 2 Count (Hi)]] |
− | | | + | | TMR2_CNT_H |
| colspan="8" style="background-color:#00FFFF;"| Count | | colspan="8" style="background-color:#00FFFF;"| Count | ||
|- | |- | ||
| $40 | | $40 | ||
− | | 256Hz Timer Control | + | | [[256Hz Timer|256Hz Timer Control]] |
− | | | + | | TMR256_CTRL |
| colspan="6" style="border:none;background-color:#808080;"| | | colspan="6" style="border:none;background-color:#808080;"| | ||
| style="background-color:#FFFF00;"| Reset | | style="background-color:#FFFF00;"| Reset | ||
Line 345: | Line 367: | ||
|- | |- | ||
| $41 | | $41 | ||
− | | 256Hz Timer Counter | + | | [[256Hz Timer|256Hz Timer Counter]] |
− | | | + | | TMR256_CNT |
| colspan="8" style="background-color:#00FFFF;"| Count | | colspan="8" style="background-color:#00FFFF;"| Count | ||
|- | |- | ||
| $44 | | $44 | ||
+ | | Unknown | ||
+ | | style="border:none;"| | ||
+ | | colspan="4" style="background-color:#C0FF00;"| ??? | ||
+ | | style="background-color:#C0C0C0;"| ??? | ||
+ | | colspan="3" style="background-color:#C0FF00;"| ??? | ||
|- | |- | ||
| $45 | | $45 | ||
+ | | Unknown | ||
+ | | style="border:none;"| | ||
+ | | colspan="4" style="background-color:#C0C0C0;"| ??? | ||
+ | | style="background-color:#C0FFC0;"| ??? | ||
+ | | style="background-color:#C0FF00;"| ??? | ||
+ | | style="background-color:#C0FFC0;"| ??? | ||
+ | | style="background-color:#C0FF00;"| ??? | ||
|- | |- | ||
| $46 | | $46 | ||
+ | | Unknown | ||
+ | | style="border:none;"| | ||
+ | | colspan="8" style="background-color:#C0FF00;"| ??? | ||
|- | |- | ||
| $47 | | $47 | ||
+ | | Unknown | ||
+ | | style="border:none;"| | ||
+ | | colspan="4" style="background-color:#C0C0C0;"| ??? | ||
+ | | colspan="4" style="background-color:#C0FF00;"| ??? | ||
|- | |- | ||
| $48 | | $48 | ||
− | | Timer 3 Control (Lo) | + | | [[Timers|Timer 3 Control (Lo)]] |
− | | | + | | TMR3_CTRL_L |
| style="background-color:#80FF80;"| 16-bit Mode | | style="background-color:#80FF80;"| 16-bit Mode | ||
| colspan="3" style="border:none;background-color:#808080;"| | | colspan="3" style="border:none;background-color:#808080;"| | ||
Line 368: | Line 409: | ||
|- | |- | ||
| $49 | | $49 | ||
− | | Timer 3 Control (Hi) | + | | [[Timers|Timer 3 Control (Hi)]] |
− | | | + | | TMR3_CTRL_H |
| colspan="4" style="border:none;background-color:#808080;"| | | colspan="4" style="border:none;background-color:#808080;"| | ||
| style="background-color:#80FF80;"| ??? | | style="background-color:#80FF80;"| ??? | ||
Line 377: | Line 418: | ||
|- | |- | ||
| $4A | | $4A | ||
− | | Timer 3 Preset (Lo) | + | | [[Timers|Timer 3 Preset (Lo)]] |
− | | | + | | TMR3_PRE_L |
| colspan="8" style="background-color:#80FF80;"| Preset | | colspan="8" style="background-color:#80FF80;"| Preset | ||
|- | |- | ||
| $4B | | $4B | ||
− | | Timer 3 Preset (Hi) | + | | [[Timers|Timer 3 Preset (Hi)]] |
− | | | + | | TMR3_PRE_H |
| colspan="8" style="background-color:#80FF80;"| Preset | | colspan="8" style="background-color:#80FF80;"| Preset | ||
|- | |- | ||
| $4C | | $4C | ||
− | | Timer 3 Pivot (Lo) | + | | [[Timers|Timer 3 Pivot (Lo)]] |
− | | | + | | TMR3_PVT_L |
| colspan="8" style="background-color:#80FF80;"| Pivot | | colspan="8" style="background-color:#80FF80;"| Pivot | ||
|- | |- | ||
| $4D | | $4D | ||
− | | Timer 3 Pivot (Hi) | + | | [[Timers|Timer 3 Pivot (Hi)]] |
− | | | + | | TMR3_PVT_H |
| colspan="8" style="background-color:#80FF80;"| Pivot | | colspan="8" style="background-color:#80FF80;"| Pivot | ||
|- | |- | ||
| $4E | | $4E | ||
− | | Timer 3 Count (Lo) | + | | [[Timers|Timer 3 Count (Lo)]] |
− | | | + | | TMR3_CNT_L |
| colspan="8" style="background-color:#00FFFF;"| Count | | colspan="8" style="background-color:#00FFFF;"| Count | ||
|- | |- | ||
| $4F | | $4F | ||
− | | Timer 3 Count (Hi) | + | | [[Timers|Timer 3 Count (Hi)]] |
− | | | + | | TMR3_CNT_H |
| colspan="8" style="background-color:#00FFFF;"| Count | | colspan="8" style="background-color:#00FFFF;"| Count | ||
|- | |- | ||
| $50 | | $50 | ||
+ | | Unknown | ||
+ | | style="border:none;"| | ||
+ | | colspan="8" style="background-color:#C0FF00;"| ??? | ||
|- | |- | ||
| $51 | | $51 | ||
+ | | Unknown | ||
+ | | style="border:none;"| | ||
+ | | colspan="6" style="background-color:#C0C0C0;"| ??? | ||
+ | | colspan="2" style="background-color:#C0FF00;"| ??? | ||
|- | |- | ||
| $52 | | $52 | ||
Line 423: | Line 471: | ||
|- | |- | ||
| $53 | | $53 | ||
+ | | Cart Bus | ||
+ | | CART_BUS | ||
+ | | colspan="6" style="border:none;background-color:#808080;"| | ||
+ | | style="background-color:#00FFFF;"| CARD_N | ||
+ | | style="border:none;background-color:#808080;"| | ||
|- | |- | ||
| $54 | | $54 | ||
+ | | Unknown | ||
+ | | style="border:none;"| | ||
+ | | style="background-color:#C0C0C0;"| ??? | ||
+ | | colspan="3" style="background-color:#C0FF00;"| ??? | ||
+ | | style="background-color:#C0C0C0;"| ??? | ||
+ | | colspan="3" style="background-color:#C0FF00;"| ??? | ||
|- | |- | ||
| $55 | | $55 | ||
+ | | Unknown | ||
+ | | style="border:none;"| | ||
+ | | colspan="5" style="background-color:#C0C0C0;"| ??? | ||
+ | | colspan="3" style="background-color:#C0FF00;"| ??? | ||
|- | |- | ||
| $60 | | $60 | ||
− | | I/O Direction Select | + | | [[PM I/O Port|I/O Direction Select]] |
| IO_DIR | | IO_DIR | ||
− | | style="background-color:#80FF80;"| ?? | + | | style="background-color:#80FF80;"| ??? |
− | | style="background-color:#80FF80;"| ?? | + | | style="background-color:#80FF80;"| ??? |
| style="background-color:#80FF80;"| IR Disable | | style="background-color:#80FF80;"| IR Disable | ||
| style="background-color:#80FF80;"| Rumble | | style="background-color:#80FF80;"| Rumble | ||
Line 441: | Line 504: | ||
|- | |- | ||
| $61 | | $61 | ||
− | | I/O Data Register | + | | [[PM I/O Port|I/O Data Register]] |
| IO_DATA | | IO_DATA | ||
− | | style="background-color:#80FF80;"| ?? | + | | style="background-color:#80FF80;"| ??? |
− | | style="background-color:#80FF80;"| ?? | + | | style="background-color:#80FF80;"| ??? |
| style="background-color:#80FF80;"| IR Disable | | style="background-color:#80FF80;"| IR Disable | ||
| style="background-color:#80FF80;"| Rumble | | style="background-color:#80FF80;"| Rumble | ||
Line 453: | Line 516: | ||
|- | |- | ||
| $62 | | $62 | ||
+ | | Unknown | ||
+ | | style="border:none;"| | ||
+ | | colspan="4" style="background-color:#C0FF00;"| ??? | ||
+ | | colspan="4" style="background-color:#C0C0C0;"| ??? | ||
|- | |- | ||
| $70 | | $70 | ||
− | | | + | | [[PM Audio|Audio Control]] |
− | | | + | | AUD_CTRL |
| colspan="5" style="border:none;background-color:#808080;"| | | colspan="5" style="border:none;background-color:#808080;"| | ||
− | | style="background-color:#80FF80;"| ?? | + | | style="background-color:#80FF80;"| ??? |
− | | | + | | colspan="2" style="background-color:#80FF80;"| Mutes audio if not 0!? |
− | |||
|- | |- | ||
| $71 | | $71 | ||
− | | Audio Volume | + | | [[PM Audio|Audio Volume]] |
| AUD_VOL | | AUD_VOL | ||
| colspan="5" style="border:none;background-color:#808080;"| | | colspan="5" style="border:none;background-color:#808080;"| | ||
− | | style="background-color:#80FF80;"| | + | | style="background-color:#80FF80;"| Cart Power (1=Off;0=On) |
| colspan="2" style="background-color:#80FF80;"| Volume | | colspan="2" style="background-color:#80FF80;"| Volume | ||
|- | |- | ||
Line 481: | Line 547: | ||
| $81 | | $81 | ||
| [[PM PRC|PRC Rate Control]] | | [[PM PRC|PRC Rate Control]] | ||
− | | | + | | PRC_RATE |
| colspan="4" style="background-color:#00FFFF;"| Frame counter | | colspan="4" style="background-color:#00FFFF;"| Frame counter | ||
| colspan="3" style="background-color:#80FF80;"| Rate divider | | colspan="3" style="background-color:#80FF80;"| Rate divider | ||
Line 487: | Line 553: | ||
|- | |- | ||
| $82 | | $82 | ||
− | | [[PM PRC|PRC Map Tile Base | + | | [[PM PRC|PRC Map Tile Base Low]] |
| PRC_MAP_LO | | PRC_MAP_LO | ||
| colspan="5" style="background-color:#80FF80;"| Map Tile Base | | colspan="5" style="background-color:#80FF80;"| Map Tile Base | ||
Line 493: | Line 559: | ||
|- | |- | ||
| $83 | | $83 | ||
− | | [[PM PRC|PRC Map Tile Base | + | | [[PM PRC|PRC Map Tile Base Middle]] |
| PRC_MAP_MID | | PRC_MAP_MID | ||
| colspan="8" style="background-color:#80FF80;"| Map Tile Base | | colspan="8" style="background-color:#80FF80;"| Map Tile Base | ||
|- | |- | ||
| $84 | | $84 | ||
− | | [[PM PRC|PRC Map Tile Base | + | | [[PM PRC|PRC Map Tile Base High]] |
| PRC_MAP_HI | | PRC_MAP_HI | ||
| colspan="3" style="border:none;background-color:#808080;"| | | colspan="3" style="border:none;background-color:#808080;"| | ||
Line 516: | Line 582: | ||
|- | |- | ||
| $87 | | $87 | ||
− | | [[PM PRC|PRC Sprite Tile Base | + | | [[PM PRC|PRC Sprite Tile Base Low]] |
| PRC_SPR_LO | | PRC_SPR_LO | ||
| colspan="2" style="background-color:#80FF80;"| Sprite Tile Base | | colspan="2" style="background-color:#80FF80;"| Sprite Tile Base | ||
Line 522: | Line 588: | ||
|- | |- | ||
| $88 | | $88 | ||
− | | [[PM PRC|PRC Sprite Tile Base | + | | [[PM PRC|PRC Sprite Tile Base Middle]] |
| PRC_SPR_MID | | PRC_SPR_MID | ||
| colspan="8" style="background-color:#80FF80;"| Sprite Tile Base | | colspan="8" style="background-color:#80FF80;"| Sprite Tile Base | ||
|- | |- | ||
| $89 | | $89 | ||
− | | [[PM PRC|PRC Sprite Tile Base | + | | [[PM PRC|PRC Sprite Tile Base Hi]] |
| PRC_SPR_HI | | PRC_SPR_HI | ||
| colspan="3" style="border:none;background-color:#808080;"| | | colspan="3" style="border:none;background-color:#808080;"| | ||
Line 535: | Line 601: | ||
| [[PM PRC|PRC Counter]] | | [[PM PRC|PRC Counter]] | ||
| PRC_CNT | | PRC_CNT | ||
− | | | + | | style="border:none;background-color:#808080;"| |
− | | colspan=" | + | | colspan="7" style="background-color:#00FFFF;"| Count |
|- | |- | ||
| $8B | | $8B | ||
Line 606: | Line 672: | ||
| [[LCD Controller|LCD Raw Control Byte]] | | [[LCD Controller|LCD Raw Control Byte]] | ||
| LCD_CTRL | | LCD_CTRL | ||
− | |||
| colspan="8" style="background-color:#80FF80;"| LCD Control I/O | | colspan="8" style="background-color:#80FF80;"| LCD Control I/O | ||
|- | |- | ||
Line 612: | Line 677: | ||
| [[LCD Controller|LCD Raw Data Byte]] | | [[LCD Controller|LCD Raw Data Byte]] | ||
| LCD_DATA | | LCD_DATA | ||
− | |||
| colspan="8" style="background-color:#80FF80;"| LCD Data I/O | | colspan="8" style="background-color:#80FF80;"| LCD Data I/O | ||
|} | |} |
Latest revision as of 03:50, 30 May 2011
Register Overview
The Pokemon Mini maps $2000 ~ $20FF as hardware control registers. This area is reserved for hardware related functions such as video, audio, general purpose timers, hardware I/O and system control.
Much of this address space is mapped as Open-Bus, leading us to beleive that this area is not used for any purpose. Other areas respond to requests but their purpose is yet undetermined.
Registers tend to be controlled on a bit level, so for the sanity purposes, they will be broken down to this level. At any point they are shown spanning multiple columns, that indicates that it is a multi-bit value and should be treated as if they were a number.
The bits themselves come in four flavors: Read-only, Write-Only, Read-Write, and S-R Strobe. Write-Only registers typically return a zero value, and are generally only used for things such as resetting timers. S-R Strobes are used for clearing interrupt events, writting a logical '1' to any bit that is set will result in a bit being cleared, where as '0' leaves them unchanged. Unused bits always return '0'.
Any register not included on this list reads as Open-Bus and will be excluded unless a function has otherwise been determined.
Register Mapping
Unused | Read/Write | Read Only | Write Only | S-R Strobe | Read/Write (BIOS, Software only) | Unknown (Read/Write) | Unknown (Weird) | Unknown (Unused) |
Address | Register | Const Name | < Bit 7 > | < Bit 6 > | < Bit 5 > | < Bit 4 > | < Bit 3 > | < Bit 2 > | < Bit 1 > | < Bit 0 > |
---|---|---|---|---|---|---|---|---|---|---|
$00 | System Control 1 | SYS_CTRL1 | Startup Contrast | Cartridge I/O Enable |
LCD I/O Enable | |||||
$01 | System Control 2 | SYS_CTRL2 | Ram vector | Int abort | Enable cart interrupts | Power on reset | Cart type | |||
$02 | System Control 3 | SYS_CTRL3 | Cart power state | Cart power required | Suspend mode | ??? | RTC Timer valid | ??? | ||
$08 | Second Counter Control | SEC_CTRL | Reset | Enable | ||||||
$09 | Second Counter Low | SEC_CNT_LO | Counter | |||||||
$0A | Second Counter Middle | SEC_CNT_MID | Counter | |||||||
$0B | Second Counter High | SEC_CNT_HI | Counter | |||||||
$10 | Battery Sensor | SYS_BATT | Low Battery | Battery ADC control | Battery ADC threshold value | |||||
$18 | Timer 1 Prescalars | TMR1_SCALE | Enable Hi | Hi Scalar | Enable Lo | Lo Scalar | ||||
$19 | Timers Osc. Enable Timer 1 Osc. Select |
TMR1_ENA_OSC TMR1_OSC |
Enable Osc. 1 | Enable Osc. 2 | 2nd Osc. (Hi) | 2nd Osc. (Lo) | ||||
$1A | Timer 2 Prescalars | TMR2_SCALE | Enable Hi | Hi Scalar | Enable Lo | Lo Scalar | ||||
$1B | Timer 2 Osc. Select | TMR2_OSC | 2nd Osc. (Hi) | 2nd Osc. (Lo) | ||||||
$1C | Timer 3 Prescalars | TMR3_SCALE | Enable Hi | Hi Scalar | Enable Lo | Lo Scalar | ||||
$1D | Timer 3 Osc. Select | TMR3_OSC | 2nd Osc. (Hi) | 2nd Osc. (Lo) | ||||||
$20 | IRQ Priority 1 | IRQ_PRI1 | IRQ $03 ~ $04 | IRQ $05 ~ $06 | IRQ $07 ~ $08 | IRQ $09 ~ $0A | ||||
$21 | IRQ Priority 2 | IRQ_PRI2 | IRQ $0B ~ $0E | IRQ $13 ~ $14 | IRQ $15 ~ $1C | IRQ ??? ($1D ~ $1F?) | ||||
$22 | IRQ Priority 3 | IRQ_PRI3 | IRQ $0F~$10 | |||||||
$23 | IRQ Enable 1 | IRQ_ENA1 | IRQ $03 | IRQ $04 | IRQ $05 | IRQ $06 | IRQ $07 | IRQ $08 | IRQ $09 | IRQ $0A |
$24 | IRQ Enable 2 | IRQ_ENA2 | IRQ $0B | IRQ $0C | IRQ $0D | IRQ $0E | IRQ $13 | IRQ $14 | ||
$25 | IRQ Enable 3 | IRQ_ENA3 | IRQ $15 | IRQ $16 | IRQ $17 | IRQ $18 | IRQ $19 | IRQ $1A | IRQ $1B | IRQ $1C |
$26 | IRQ Enable 4 | IRQ_ENA4 | IRQ $0F | IRQ $10 | IRQ ??? | IRQ ??? | IRQ $1D | IRQ $1E | IRQ $1F | |
$27 | IRQ Active 1 | IRQ_ACT1 | IRQ $03 | IRQ $04 | IRQ $05 | IRQ $06 | IRQ $07 | IRQ $08 | IRQ $09 | IRQ $0A |
$28 | IRQ Active 2 | IRQ_ACT2 | IRQ $0B | IRQ $0C | IRQ $0D | IRQ $0E | IRQ $13 | IRQ $14 | ||
$29 | IRQ Active 3 | IRQ_ACT3 | IRQ $15 | IRQ $16 | IRQ $17 | IRQ $18 | IRQ $19 | IRQ $1A | IRQ $1B | IRQ $1C |
$2A | IRQ Active 4 | IRQ_ACT4 | IRQ $0F | IRQ $10 | IRQ ??? | IRQ ??? | IRQ $1D | IRQ $1E | IRQ $1F | |
$30 | Timer 1 Control (Lo) | TMR1_CTRL_L | 16-bit Mode | ??? | Enable | Reset | ??? | |||
$31 | Timer 1 Control (Hi) | TMR1_CTRL_H | ??? | Enable | Reset | ??? | ||||
$32 | Timer 1 Preset (Lo) | TMR1_PRE_L | Preset | |||||||
$33 | Timer 1 Preset (Hi) | TMR1_PRE_H | Preset | |||||||
$34 | Timer 1 Pivot (Lo) | TMR1_PVT_L | Pivot | |||||||
$35 | Timer 1 Pivot (Hi) | TMR1_PVT_H | Pivot | |||||||
$36 | Timer 1 Count (Lo) | TMR1_CNT_L | Count | |||||||
$37 | Timer 1 Count (Hi) | TMR1_CNT_H | Count | |||||||
$38 | Timer 2 Control (Lo) | TMR2_CTRL_L | 16-bit Mode | ??? | Enable | Reset | ??? | |||
$39 | Timer 2 Control (Hi) | TMR2_CTRL_H | ??? | Enable | Reset | ??? | ||||
$3A | Timer 2 Preset (Lo) | TMR2_PRE_L | Preset | |||||||
$3B | Timer 2 Preset (Hi) | TMR2_PRE_H | Preset | |||||||
$3C | Timer 2 Pivot (Lo) | TMR2_PVT_L | Pivot | |||||||
$3D | Timer 2 Pivot (Hi) | TMR2_PVT_H | Pivot | |||||||
$3E | Timer 2 Count (Lo) | TMR2_CNT_L | Count | |||||||
$3F | Timer 2 Count (Hi) | TMR2_CNT_H | Count | |||||||
$40 | 256Hz Timer Control | TMR256_CTRL | Reset | Enable | ||||||
$41 | 256Hz Timer Counter | TMR256_CNT | Count | |||||||
$44 | Unknown | ??? | ??? | ??? | ||||||
$45 | Unknown | ??? | ??? | ??? | ??? | ??? | ||||
$46 | Unknown | ??? | ||||||||
$47 | Unknown | ??? | ??? | |||||||
$48 | Timer 3 Control (Lo) | TMR3_CTRL_L | 16-bit Mode | ??? | Enable | Reset | ??? | |||
$49 | Timer 3 Control (Hi) | TMR3_CTRL_H | ??? | Enable | Reset | ??? | ||||
$4A | Timer 3 Preset (Lo) | TMR3_PRE_L | Preset | |||||||
$4B | Timer 3 Preset (Hi) | TMR3_PRE_H | Preset | |||||||
$4C | Timer 3 Pivot (Lo) | TMR3_PVT_L | Pivot | |||||||
$4D | Timer 3 Pivot (Hi) | TMR3_PVT_H | Pivot | |||||||
$4E | Timer 3 Count (Lo) | TMR3_CNT_L | Count | |||||||
$4F | Timer 3 Count (Hi) | TMR3_CNT_H | Count | |||||||
$50 | Unknown | ??? | ||||||||
$51 | Unknown | ??? | ??? | |||||||
$52 | Key-Pad Status (Active 0) | KEY_PAD | Power | Right | Left | Down | Up | C | B | A |
$53 | Cart Bus | CART_BUS | CARD_N | |||||||
$54 | Unknown | ??? | ??? | ??? | ??? | |||||
$55 | Unknown | ??? | ??? | |||||||
$60 | I/O Direction Select | IO_DIR | ??? | ??? | IR Disable | Rumble | EEPROM Clock | EEPROM Data | IR Rx | IR Tx |
$61 | I/O Data Register | IO_DATA | ??? | ??? | IR Disable | Rumble | EEPROM Clock | EEPROM Data | IR Rx | IR Tx |
$62 | Unknown | ??? | ??? | |||||||
$70 | Audio Control | AUD_CTRL | ??? | Mutes audio if not 0!? | ||||||
$71 | Audio Volume | AUD_VOL | Cart Power (1=Off;0=On) | Volume | ||||||
$80 | PRC Stage Control | PRC_MODE | Map Size | Ena Copy | Ena Sprites | Ena Map | Invert Map | |||
$81 | PRC Rate Control | PRC_RATE | Frame counter | Rate divider | ??? | |||||
$82 | PRC Map Tile Base Low | PRC_MAP_LO | Map Tile Base | |||||||
$83 | PRC Map Tile Base Middle | PRC_MAP_MID | Map Tile Base | |||||||
$84 | PRC Map Tile Base High | PRC_MAP_HI | Map Tile Base | |||||||
$85 | PRC Map Vertical Scroll | PRC_SCROLL_Y | Map Scroll Y | |||||||
$86 | PRC Map Horizontal Scroll | PRC_SCROLL_X | Map Scroll X | |||||||
$87 | PRC Sprite Tile Base Low | PRC_SPR_LO | Sprite Tile Base | |||||||
$88 | PRC Sprite Tile Base Middle | PRC_SPR_MID | Sprite Tile Base | |||||||
$89 | PRC Sprite Tile Base Hi | PRC_SPR_HI | Sprite Tile Base | |||||||
$8A | PRC Counter | PRC_CNT | Count | |||||||
$8B | Unknown (returns 0) | |||||||||
$8C | Unknown (returns 0) | |||||||||
$8D | Unknown (returns 0) | |||||||||
$8E | Unknown (returns 0) | |||||||||
$8F | Unknown (returns 0) | |||||||||
$F0 | Unknown (returns 0) | |||||||||
$F1 | Unknown (returns 0) | |||||||||
$F2 | Unknown (returns 0) | |||||||||
$F3 | Unknown (returns 0) | |||||||||
$F4 | Unknown (returns 0) | |||||||||
$F5 | Unknown (returns 0) | |||||||||
$F6 | Unknown (returns 0) | |||||||||
$F7 | Unknown (returns 0) | |||||||||
$FE | LCD Raw Control Byte | LCD_CTRL | LCD Control I/O | |||||||
$FF | LCD Raw Data Byte | LCD_DATA | LCD Data I/O |