Difference between revisions of "PM Registers"
(→Register Mapping) |
(→Register Mapping) |
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Line 29: | Line 29: | ||
| System Control 1 | | System Control 1 | ||
| SYS_CTL1 | | SYS_CTL1 | ||
− | | colspan="6"| Startup Contrast | + | | colspan="6" style="background-color:#80FF80;"| Startup Contrast |
− | | | + | | style="background-color:#80FF80;"| ??? |
− | | | + | | style="background-color:#80FF80;"| ??? |
|- | |- | ||
| $01 | | $01 | ||
Line 42: | Line 42: | ||
| colspan="6" style="border:none;"| | | colspan="6" style="border:none;"| | ||
| style="background-color:#FFFF00;"| Reset | | style="background-color:#FFFF00;"| Reset | ||
− | | Enable | + | | style="background-color:#80FF80;"| Enable |
|- | |- | ||
| $09 | | $09 | ||
Line 62: | Line 62: | ||
| Battery Sensor | | Battery Sensor | ||
| SYS_BATT | | SYS_BATT | ||
− | | colspan="2"| | + | | colspan="2" style="border:none;"| |
| style="background-color:#00FFFF;" | Low Battery | | style="background-color:#00FFFF;" | Low Battery | ||
− | | colspan="5"| ?? (Low-Level?) | + | | colspan="5" style="background-color:#80FF80;"| ?? (Low-Level?) |
|- | |- | ||
| $18 | | $18 | ||
| Timer 1 Prescalars | | Timer 1 Prescalars | ||
| TIM1_SCALE | | TIM1_SCALE | ||
− | | Enable Hi | + | | style="background-color:#80FF80;"| Enable Hi |
− | | colspan="3"| Hi Scalar | + | | colspan="3" style="background-color:#80FF80;"| Hi Scalar |
− | | Enable Low | + | | style="background-color:#80FF80;"| Enable Low |
− | | colspan="3"| Low Scalar | + | | colspan="3" style="background-color:#80FF80;"| Low Scalar |
|- | |- | ||
| $19 | | $19 | ||
Line 78: | Line 78: | ||
| TIM1_SPEED_ENA | | TIM1_SPEED_ENA | ||
| colspan="2" style="border:none;"| | | colspan="2" style="border:none;"| | ||
− | | Enable Fast | + | | style="background-color:#80FF80;"| Enable Fast |
− | | Enable Slow | + | | style="background-color:#80FF80;"| Enable Slow |
| colspan="2" style="border:none;"| | | colspan="2" style="border:none;"| | ||
− | | Slow (Hi) | + | | style="background-color:#80FF80;"| Slow (Hi) |
− | | Slow (Lo) | + | | style="background-color:#80FF80;"| Slow (Lo) |
|- | |- | ||
| $1A | | $1A | ||
| Timer 2 Prescalars | | Timer 2 Prescalars | ||
| TIM2_SCALE | | TIM2_SCALE | ||
− | | Enable Hi | + | | style="background-color:#80FF80;"| Enable Hi |
− | | colspan="3"| Hi Scalar | + | | colspan="3" style="background-color:#80FF80;"| Hi Scalar |
− | | Enable Low | + | | style="background-color:#80FF80;"| Enable Low |
− | | colspan="3"| Low Scalar | + | | colspan="3" style="background-color:#80FF80;"| Low Scalar |
|- | |- | ||
| $1B | | $1B | ||
Line 96: | Line 96: | ||
| TIM2_SPEED | | TIM2_SPEED | ||
| colspan="6" style="border:none;"| | | colspan="6" style="border:none;"| | ||
− | | Slow (Hi) | + | | style="background-color:#80FF80;"| Slow (Hi) |
− | | Slow (Lo) | + | | style="background-color:#80FF80;"| Slow (Lo) |
|- | |- | ||
| $1C | | $1C | ||
| Timer 3 Prescalars | | Timer 3 Prescalars | ||
| TIM3_SCALE | | TIM3_SCALE | ||
− | | Enable Hi | + | | style="background-color:#80FF80;"| Enable Hi |
− | | colspan="3"| Hi Scalar | + | | colspan="3" style="background-color:#80FF80;"| Hi Scalar |
− | | Enable Low | + | | style="background-color:#80FF80;"| Enable Low |
− | | colspan="3"| Low Scalar | + | | colspan="3" style="background-color:#80FF80;"| Low Scalar |
|- | |- | ||
| $1D | | $1D | ||
Line 111: | Line 111: | ||
| TIM3_SPEED | | TIM3_SPEED | ||
| colspan="6" style="border:none;"| | | colspan="6" style="border:none;"| | ||
− | | Slow (Hi) | + | | style="background-color:#80FF80;"| Slow (Hi) |
− | | Slow (Lo) | + | | style="background-color:#80FF80;"| Slow (Lo) |
|- | |- | ||
| $20 | | $20 | ||
| IRQ Priority 1 | | IRQ Priority 1 | ||
| IRQ_PRI_1 | | IRQ_PRI_1 | ||
− | | colspan="2"| IRQ $03 ~ $04 | + | | colspan="2" style="background-color:#80FF80;"| IRQ $03 ~ $04 |
− | | colspan="2"| IRQ $05 ~ $06 | + | | colspan="2" style="background-color:#80FF80;"| IRQ $05 ~ $06 |
− | | colspan="2"| IRQ $07 ~ $08 | + | | colspan="2" style="background-color:#80FF80;"| IRQ $07 ~ $08 |
− | | colspan="2"| IRQ $09 ~ $0A | + | | colspan="2" style="background-color:#80FF80;"| IRQ $09 ~ $0A |
|- | |- | ||
| $21 | | $21 | ||
| IRQ Priority 2 | | IRQ Priority 2 | ||
| IRQ_PRI_2 | | IRQ_PRI_2 | ||
− | | colspan="2"| IRQ $0B ~ $0E | + | | colspan="2" style="background-color:#80FF80;"| IRQ $0B ~ $0E |
− | | colspan="2"| IRQ $13 ~ $14 | + | | colspan="2" style="background-color:#80FF80;"| IRQ $13 ~ $14 |
− | | colspan="2"| IRQ $15 ~ $1C | + | | colspan="2" style="background-color:#80FF80;"| IRQ $15 ~ $1C |
− | | colspan="2"| IRQ ?? ($1D ~ $1F?) | + | | colspan="2" style="background-color:#80FF80;"| IRQ ?? ($1D ~ $1F?) |
|- | |- | ||
| $22 | | $22 | ||
Line 134: | Line 134: | ||
| IRQ_PRI_3 | | IRQ_PRI_3 | ||
| colspan="6" style="border:none;"| | | colspan="6" style="border:none;"| | ||
− | | colspan="2"| IRQ $0F~$10 | + | | colspan="2" style="background-color:#80FF80;"| IRQ $0F~$10 |
|- | |- | ||
| $23 | | $23 | ||
| IRQ Enable 1 | | IRQ Enable 1 | ||
| IRQ_ENA_1 | | IRQ_ENA_1 | ||
− | | IRQ $03 | + | | style="background-color:#80FF80;"| IRQ $03 |
− | | IRQ $04 | + | | style="background-color:#80FF80;"| IRQ $04 |
− | | IRQ $05 | + | | style="background-color:#80FF80;"| IRQ $05 |
− | | IRQ $06 | + | | style="background-color:#80FF80;"|IRQ $06 |
− | | IRQ $07 | + | | style="background-color:#80FF80;"|IRQ $07 |
− | | IRQ $08 | + | | style="background-color:#80FF80;"|IRQ $08 |
− | | IRQ $09 | + | | style="background-color:#80FF80;"|IRQ $09 |
− | | IRQ $0A | + | | style="background-color:#80FF80;"|IRQ $0A |
|- | |- | ||
| $24 | | $24 | ||
Line 152: | Line 152: | ||
| IRQ_ENA_2 | | IRQ_ENA_2 | ||
| colspan="2" style="border:none;"| | | colspan="2" style="border:none;"| | ||
− | | IRQ $0B | + | | style="background-color:#80FF80;"|IRQ $0B |
− | | IRQ $0C | + | | style="background-color:#80FF80;"|IRQ $0C |
− | | IRQ $0D | + | | style="background-color:#80FF80;"|IRQ $0D |
− | | IRQ $0E | + | | style="background-color:#80FF80;"|IRQ $0E |
− | | IRQ $13 | + | | style="background-color:#80FF80;"|IRQ $13 |
− | | IRQ $14 | + | | style="background-color:#80FF80;"|IRQ $14 |
|- | |- | ||
| $25 | | $25 | ||
| IRQ Enable 3 | | IRQ Enable 3 | ||
| IRQ_ENA_3 | | IRQ_ENA_3 | ||
− | | IRQ $15 | + | | style="background-color:#80FF80;"|IRQ $15 |
− | | IRQ $16 | + | | style="background-color:#80FF80;"|IRQ $16 |
− | | IRQ $17 | + | | style="background-color:#80FF80;"|IRQ $17 |
− | | IRQ $18 | + | | style="background-color:#80FF80;"|IRQ $18 |
− | | IRQ $19 | + | | style="background-color:#80FF80;"|IRQ $19 |
− | | IRQ $1A | + | | style="background-color:#80FF80;"|IRQ $1A |
− | | IRQ $1B | + | | style="background-color:#80FF80;"|IRQ $1B |
− | | IRQ $1C | + | | style="background-color:#80FF80;"|IRQ $1C |
|- | |- | ||
| $26 | | $26 | ||
| IRQ Enable 4 | | IRQ Enable 4 | ||
| IRQ_ENA_4 | | IRQ_ENA_4 | ||
− | | IRQ $0F | + | | style="background-color:#80FF80;"|IRQ $0F |
− | | IRQ $10 | + | | style="background-color:#80FF80;"|IRQ $10 |
− | | IRQ ?? | + | | style="background-color:#80FF80;"|IRQ ?? |
− | | IRQ ?? | + | | style="background-color:#80FF80;"|IRQ ?? |
| style="border:none;"| | | style="border:none;"| | ||
− | | IRQ $1D | + | | style="background-color:#80FF80;"|IRQ $1D |
− | | IRQ $1E | + | | style="background-color:#80FF80;"|IRQ $1E |
− | | IRQ $1F | + | | style="background-color:#80FF80;"|IRQ $1F |
|- | |- | ||
| $27 | | $27 | ||
Line 233: | Line 233: | ||
| Timer 1 Control (Lo) | | Timer 1 Control (Lo) | ||
| TIM1_CTL_L | | TIM1_CTL_L | ||
− | | 16-bit Mode | + | | style="background-color:#80FF80;"| 16-bit Mode |
| colspan="3" style="border:none;"| | | colspan="3" style="border:none;"| | ||
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
− | | Enable | + | | style="background-color:#80FF80;"| Enable |
| style="background-color:#FFFF00;"| Reset | | style="background-color:#FFFF00;"| Reset | ||
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
|- | |- | ||
| $31 | | $31 | ||
Line 244: | Line 244: | ||
| TIM1_CTL_H | | TIM1_CTL_H | ||
| colspan="4" style="border:none;"| | | colspan="4" style="border:none;"| | ||
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
− | | Enable | + | | style="background-color:#80FF80;"| Enable |
| style="background-color:#FFFF00;"| Reset | | style="background-color:#FFFF00;"| Reset | ||
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
|- | |- | ||
| $32 | | $32 | ||
| Timer 1 Preset (Lo) | | Timer 1 Preset (Lo) | ||
| TIM1_PRE_L | | TIM1_PRE_L | ||
− | | colspan="8"| Preset | + | | colspan="8" style="background-color:#80FF80;"| Preset |
|- | |- | ||
| $33 | | $33 | ||
| Timer 1 Preset (Hi) | | Timer 1 Preset (Hi) | ||
| TIM1_PRE_H | | TIM1_PRE_H | ||
− | | colspan="8"| Preset | + | | colspan="8" style="background-color:#80FF80;"| Preset |
|- | |- | ||
| $34 | | $34 | ||
| Timer 1 Pivot (Lo) | | Timer 1 Pivot (Lo) | ||
| TIM1_PVT_L | | TIM1_PVT_L | ||
− | | colspan="8"| Pivot | + | | colspan="8" style="background-color:#80FF80;"| Pivot |
|- | |- | ||
| $35 | | $35 | ||
| Timer 1 Pivot (Hi) | | Timer 1 Pivot (Hi) | ||
| TIM1_PVT_H | | TIM1_PVT_H | ||
− | | colspan="8"| Pivot | + | | colspan="8" style="background-color:#80FF80;"| Pivot |
|- | |- | ||
| $36 | | $36 | ||
Line 282: | Line 282: | ||
| Timer 2 Control (Lo) | | Timer 2 Control (Lo) | ||
| TIM2_CTL_L | | TIM2_CTL_L | ||
− | | 16-bit Mode | + | | style="background-color:#80FF80;"| 16-bit Mode |
| colspan="3" style="border:none;"| | | colspan="3" style="border:none;"| | ||
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
− | | Enable | + | | style="background-color:#80FF80;"| Enable |
| style="background-color:#FFFF00;"| Reset | | style="background-color:#FFFF00;"| Reset | ||
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
|- | |- | ||
| $39 | | $39 | ||
Line 293: | Line 293: | ||
| TIM2_CTL_H | | TIM2_CTL_H | ||
| colspan="4" style="border:none;"| | | colspan="4" style="border:none;"| | ||
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
− | | Enable | + | | style="background-color:#80FF80;"| Enable |
− | | style="background-color:#FFFF00;"| Reset | + | |style="background-color:#FFFF00;"| Reset |
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
|- | |- | ||
| $3A | | $3A | ||
| Timer 2 Preset (Lo) | | Timer 2 Preset (Lo) | ||
| TIM2_PRE_L | | TIM2_PRE_L | ||
− | | colspan="8"| Preset | + | | colspan="8" style="background-color:#80FF80;"| Preset |
|- | |- | ||
| $3B | | $3B | ||
| Timer 2 Preset (Hi) | | Timer 2 Preset (Hi) | ||
| TIM2_PRE_H | | TIM2_PRE_H | ||
− | | colspan="8"| Preset | + | | colspan="8" style="background-color:#80FF80;"| Preset |
|- | |- | ||
| $3C | | $3C | ||
| Timer 2 Pivot (Lo) | | Timer 2 Pivot (Lo) | ||
| TIM2_PVT_L | | TIM2_PVT_L | ||
− | | colspan="8"| Pivot | + | | colspan="8" style="background-color:#80FF80;"| Pivot |
|- | |- | ||
| $3D | | $3D | ||
| Timer 2 Pivot (Hi) | | Timer 2 Pivot (Hi) | ||
| TIM2_PVT_H | | TIM2_PVT_H | ||
− | | colspan="8"| Pivot | + | | colspan="8" style="background-color:#80FF80;"| Pivot |
|- | |- | ||
| $3E | | $3E | ||
Line 333: | Line 333: | ||
| colspan="6" style="border:none;"| | | colspan="6" style="border:none;"| | ||
| style="background-color:#FFFF00;"| Reset | | style="background-color:#FFFF00;"| Reset | ||
− | | Enable | + | | style="background-color:#80FF80;"| Enable |
|- | |- | ||
| $41 | | $41 | ||
Line 351: | Line 351: | ||
| Timer 3 Control (Lo) | | Timer 3 Control (Lo) | ||
| TIM3_CTL_L | | TIM3_CTL_L | ||
− | | 16-bit Mode | + | | style="background-color:#80FF80;"| 16-bit Mode |
| colspan="3" style="border:none;"| | | colspan="3" style="border:none;"| | ||
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
− | | Enable | + | | style="background-color:#80FF80;"| Enable |
| style="background-color:#FFFF00;"| Reset | | style="background-color:#FFFF00;"| Reset | ||
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
|- | |- | ||
| $49 | | $49 | ||
Line 362: | Line 362: | ||
| TIM3_CTL_H | | TIM3_CTL_H | ||
| colspan="4" style="border:none;"| | | colspan="4" style="border:none;"| | ||
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
− | | Enable | + | | style="background-color:#80FF80;"| Enable |
| style="background-color:#FFFF00;"| Reset | | style="background-color:#FFFF00;"| Reset | ||
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
|- | |- | ||
| $4A | | $4A | ||
| Timer 3 Preset (Lo) | | Timer 3 Preset (Lo) | ||
| TIM3_PRE_L | | TIM3_PRE_L | ||
− | | colspan="8"| Preset | + | | colspan="8" style="background-color:#80FF80;"| Preset |
|- | |- | ||
| $4B | | $4B | ||
| Timer 3 Preset (Hi) | | Timer 3 Preset (Hi) | ||
| TIM3_PRE_H | | TIM3_PRE_H | ||
− | | colspan="8"| Preset | + | | colspan="8" style="background-color:#80FF80;"| Preset |
|- | |- | ||
| $4C | | $4C | ||
| Timer 3 Pivot (Lo) | | Timer 3 Pivot (Lo) | ||
| TIM3_PVT_L | | TIM3_PVT_L | ||
− | | colspan="8"| Pivot | + | | colspan="8" style="background-color:#80FF80;"| Pivot |
|- | |- | ||
| $4D | | $4D | ||
| Timer 3 Pivot (Hi) | | Timer 3 Pivot (Hi) | ||
| TIM3_PVT_H | | TIM3_PVT_H | ||
− | | colspan="8"| Pivot | + | | colspan="8" style="background-color:#80FF80;"| Pivot |
|- | |- | ||
| $4E | | $4E | ||
Line 404: | Line 404: | ||
| Key-Pad Status (Active 0) | | Key-Pad Status (Active 0) | ||
| KEY_PAD | | KEY_PAD | ||
− | | Power | + | | style="background-color:#00FFFF;"| Power |
− | | Right | + | | style="background-color:#00FFFF;"| Right |
− | | Left | + | | style="background-color:#00FFFF;"| Left |
− | | Down | + | | style="background-color:#00FFFF;"| Down |
− | | Up | + | | style="background-color:#00FFFF;"| Up |
− | | C | + | | style="background-color:#00FFFF;"| C |
− | | B | + | | style="background-color:#00FFFF;"| B |
− | | A | + | | style="background-color:#00FFFF;"| A |
|- | |- | ||
| $53 | | $53 | ||
Line 422: | Line 422: | ||
| I/O Direction Select | | I/O Direction Select | ||
| IO_DIR | | IO_DIR | ||
− | | ?? | + | | style="background-color:#80FF80;"| ?? |
− | | ?? | + | | style="background-color:#80FF80;"| ?? |
− | | IR Rx Disable | + | | style="background-color:#80FF80;"| IR Rx Disable |
− | | Rumble | + | | style="background-color:#80FF80;"| Rumble |
− | | EEPROM Clock | + | | style="background-color:#80FF80;"| EEPROM Clock |
− | | EEPROM Data | + | | style="background-color:#80FF80;"| EEPROM Data |
− | | IR Rx | + | | style="background-color:#80FF80;"| IR Rx |
− | | IR Tx | + | | style="background-color:#80FF80;"| IR Tx |
|- | |- | ||
| $61 | | $61 | ||
| I/O Data Register | | I/O Data Register | ||
| IO_DATA | | IO_DATA | ||
− | | ?? | + | | style="background-color:#80FF80;"| ?? |
− | | ?? | + | | style="background-color:#80FF80;"| ?? |
− | | IR Rx Disable | + | | style="background-color:#80FF80;"| IR Rx Disable |
− | | Rumble | + | | style="background-color:#80FF80;"| Rumble |
− | | EEPROM Clock | + | | style="background-color:#80FF80;"| EEPROM Clock |
− | | EEPROM Data | + | | style="background-color:#80FF80;"| EEPROM Data |
− | | IR Rx | + | | style="background-color:#80FF80;"| IR Rx |
− | | IR Tx | + | | style="background-color:#80FF80;"| IR Tx |
|- | |- | ||
| $62 | | $62 | ||
|- | |- | ||
| $70 | | $70 | ||
− | | ??? | + | | ??? (Mutes audio if lower 2 bits != 0) |
− | | | + | | |
| colspan="5" style="border:none;"| | | colspan="5" style="border:none;"| | ||
− | | ?? | + | | style="background-color:#80FF80;"| ?? |
− | | ?? | + | | style="background-color:#80FF80;"| ?? |
− | | ?? | + | | style="background-color:#80FF80;"| ?? |
|- | |- | ||
| $71 | | $71 | ||
Line 457: | Line 457: | ||
| AUD_VOL | | AUD_VOL | ||
| colspan="5" style="border:none;"| | | colspan="5" style="border:none;"| | ||
− | | ?? | + | | style="background-color:#80FF80;"| ?? |
− | | colspan="2"|Volume (Mute,50%,50%,100% | + | | colspan="2" style="background-color:#80FF80;"|Volume (Mute,50%,50%,100%) |
|- | |- | ||
| $80 | | $80 | ||
| [[PM PRC|PRC Stage Control]] | | [[PM PRC|PRC Stage Control]] | ||
| PRC_MODE | | PRC_MODE | ||
− | | colspan="2"| | + | | colspan="2" style="border:none;"| |
− | | colspan="2"| Map Size | + | | colspan="2" style="background-color:#80FF80;"| Map Size |
− | | Ena Copy | + | | style="background-color:#80FF80;"|Ena Copy |
− | | Ena Sprites | + | | style="background-color:#80FF80;"|Ena Sprites |
− | | Ena Map | + | | style="background-color:#80FF80;"|Ena Map |
− | | Invert Map | + | | style="background-color:#80FF80;"|Invert Map |
|- | |- | ||
| $81 | | $81 | ||
Line 474: | Line 474: | ||
| PRC_SPEED | | PRC_SPEED | ||
| colspan="4" style="background-color:#00FFFF;"| Frame counter | | colspan="4" style="background-color:#00FFFF;"| Frame counter | ||
− | | colspan="3"| Rate divider | + | | colspan="3" style="background-color:#80FF80;"| Rate divider |
− | | ??? | + | | style="background-color:#80FF80;"| ??? |
|- | |- | ||
| $82 | | $82 | ||
| [[PM PRC|PRC Map Tile Base (Lo)]] | | [[PM PRC|PRC Map Tile Base (Lo)]] | ||
| PRC_MAP_LO | | PRC_MAP_LO | ||
− | | colspan="5"| Map Tile Base | + | | colspan="5" style="background-color:#80FF80;"| Map Tile Base |
| colspan="3" style="border:none;"| | | colspan="3" style="border:none;"| | ||
|- | |- | ||
Line 486: | Line 486: | ||
| [[PM PRC|PRC Map Tile Base (Mid)]] | | [[PM PRC|PRC Map Tile Base (Mid)]] | ||
| PRC_MAP_MID | | PRC_MAP_MID | ||
− | | colspan="8"| Map Tile Base | + | | colspan="8" style="background-color:#80FF80;"| Map Tile Base |
|- | |- | ||
| $84 | | $84 | ||
Line 492: | Line 492: | ||
| PRC_MAP_HI | | PRC_MAP_HI | ||
| colspan="3" style="border:none;"| | | colspan="3" style="border:none;"| | ||
− | | colspan="5"| Map Tile Base | + | | colspan="5" style="background-color:#80FF80;"| Map Tile Base |
|- | |- | ||
| $85 | | $85 | ||
Line 498: | Line 498: | ||
| PRC_SCROLL_Y | | PRC_SCROLL_Y | ||
| style="border:none;"| | | style="border:none;"| | ||
− | | colspan="7"| Map Scroll Y | + | | colspan="7" style="background-color:#80FF80;"| Map Scroll Y |
|- | |- | ||
| $86 | | $86 | ||
Line 504: | Line 504: | ||
| PRC_SCROLL_X | | PRC_SCROLL_X | ||
| style="border:none;"| | | style="border:none;"| | ||
− | | colspan="7"| Map Scroll X | + | | colspan="7" style="background-color:#80FF80;"| Map Scroll X |
|- | |- | ||
| $87 | | $87 | ||
| [[PM PRC|PRC Sprite Tile Base (Lo)]] | | [[PM PRC|PRC Sprite Tile Base (Lo)]] | ||
| PRC_SPR_LO | | PRC_SPR_LO | ||
− | | colspan="2"| Sprite Tile Base | + | | colspan="2" style="background-color:#80FF80;"| Sprite Tile Base |
| colspan="6" style="border:none;"| | | colspan="6" style="border:none;"| | ||
|- | |- | ||
Line 515: | Line 515: | ||
| [[PM PRC|PRC Sprite Tile Base (Mid)]] | | [[PM PRC|PRC Sprite Tile Base (Mid)]] | ||
| PRC_SPR_MID | | PRC_SPR_MID | ||
− | | colspan="8"| Sprite Tile Base | + | | colspan="8" style="background-color:#80FF80;"| Sprite Tile Base |
|- | |- | ||
| $89 | | $89 | ||
Line 521: | Line 521: | ||
| PRC_SPR_HI | | PRC_SPR_HI | ||
| colspan="3" style="border:none;"| | | colspan="3" style="border:none;"| | ||
− | | colspan="5"| Sprite Tile Base | + | | colspan="5" style="background-color:#80FF80;"| Sprite Tile Base |
|- | |- | ||
| $8A | | $8A | ||
Line 571: | Line 571: | ||
| [[LCD Controller|LCD Raw Control Byte]] | | [[LCD Controller|LCD Raw Control Byte]] | ||
| LCD_CTRL | | LCD_CTRL | ||
− | | colspan="8"| LCD Control I/O | + | | colspan="8" style="background-color:#80FF80;"| LCD Control I/O |
|- | |- | ||
| $FF | | $FF | ||
| [[LCD Controller|LCD Raw Data Byte]] | | [[LCD Controller|LCD Raw Data Byte]] | ||
| LCD_DATA | | LCD_DATA | ||
− | | colspan="8"| LCD Data I/O | + | | colspan="8" style="background-color:#80FF80;"| LCD Data I/O |
|} | |} |
Revision as of 05:39, 26 May 2008
Register Overview
The Pokemon Mini maps $2000 ~ $20FF as hardware control registers. This area is reserved for hardware related functions such as video, audio, general purpose timers, hardware I/O and system control.
Much of this address space is mapped as Open-Bus, leading us to beleive that this area is not used for any purpose. Other areas respond to requests but their purpose is yet undetermined.
Registers tend to be controlled on a bit level, so for the sanity purposes, they will be broken down to this level. At any point they are shown spanning multiple columns, that indicates that it is a multi-bit value and should be treated as if they were a number.
The bits themselves come in four flavors: Read-only, Write-Only, Read-Write, and S-R Strobe. Write-Only registers typically return a zero value, and are generally only used for things such as resetting timers. S-R Strobes are used for clearing interrupt events. Writting a logical '1' to any bit that is set will result in a bit being cleared, where as '0' leaves them unchanged.
Any register not included on this list reads as Open-Bus and will be excluded unless a function has otherwise been determined.
Register Mapping
Address | Register | Const Name | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|
$00 | System Control 1 | SYS_CTL1 | Startup Contrast | ??? | ??? | |||||
$01 | ||||||||||
$02 | ||||||||||
$08 | Second Counter Control | SEC_CTRL | Reset | Enable | ||||||
$09 | Second Counter Lo | SEC_CNT_LO | Counter | |||||||
$0A | Second Counter Med | SEC_CNT_MED | Counter | |||||||
$0B | Second Counter Hi | SEC_CNT_HI | Counter | |||||||
$10 | Battery Sensor | SYS_BATT | Low Battery | ?? (Low-Level?) | ||||||
$18 | Timer 1 Prescalars | TIM1_SCALE | Enable Hi | Hi Scalar | Enable Low | Low Scalar | ||||
$19 | Timer Type Enables \ Timer 1 Speeds | TIM1_SPEED_ENA | Enable Fast | Enable Slow | Slow (Hi) | Slow (Lo) | ||||
$1A | Timer 2 Prescalars | TIM2_SCALE | Enable Hi | Hi Scalar | Enable Low | Low Scalar | ||||
$1B | Timer 2 Speeds | TIM2_SPEED | Slow (Hi) | Slow (Lo) | ||||||
$1C | Timer 3 Prescalars | TIM3_SCALE | Enable Hi | Hi Scalar | Enable Low | Low Scalar | ||||
$1D | Timer 3 Speeds | TIM3_SPEED | Slow (Hi) | Slow (Lo) | ||||||
$20 | IRQ Priority 1 | IRQ_PRI_1 | IRQ $03 ~ $04 | IRQ $05 ~ $06 | IRQ $07 ~ $08 | IRQ $09 ~ $0A | ||||
$21 | IRQ Priority 2 | IRQ_PRI_2 | IRQ $0B ~ $0E | IRQ $13 ~ $14 | IRQ $15 ~ $1C | IRQ ?? ($1D ~ $1F?) | ||||
$22 | IRQ Priority 3 | IRQ_PRI_3 | IRQ $0F~$10 | |||||||
$23 | IRQ Enable 1 | IRQ_ENA_1 | IRQ $03 | IRQ $04 | IRQ $05 | IRQ $06 | IRQ $07 | IRQ $08 | IRQ $09 | IRQ $0A |
$24 | IRQ Enable 2 | IRQ_ENA_2 | IRQ $0B | IRQ $0C | IRQ $0D | IRQ $0E | IRQ $13 | IRQ $14 | ||
$25 | IRQ Enable 3 | IRQ_ENA_3 | IRQ $15 | IRQ $16 | IRQ $17 | IRQ $18 | IRQ $19 | IRQ $1A | IRQ $1B | IRQ $1C |
$26 | IRQ Enable 4 | IRQ_ENA_4 | IRQ $0F | IRQ $10 | IRQ ?? | IRQ ?? | IRQ $1D | IRQ $1E | IRQ $1F | |
$27 | IRQ Active 1 | IRQ_ACT_1 | IRQ $03 | IRQ $04 | IRQ $05 | IRQ $06 | IRQ $07 | IRQ $08 | IRQ $09 | IRQ $0A |
$28 | IRQ Active 2 | IRQ_ACT_2 | IRQ $0B | IRQ $0C | IRQ $0D | IRQ $0E | IRQ $13 | IRQ $14 | ||
$29 | IRQ Active 3 | IRQ_ACT_3 | IRQ $15 | IRQ $16 | IRQ $17 | IRQ $18 | IRQ $19 | IRQ $1A | IRQ $1B | IRQ $1C |
$2A | IRQ Active 4 | IRQ_ACT_4 | IRQ $0F | IRQ $10 | IRQ ?? | IRQ ?? | IRQ $1D | IRQ $1E | IRQ $1F | |
$30 | Timer 1 Control (Lo) | TIM1_CTL_L | 16-bit Mode | ??? | Enable | Reset | ??? | |||
$31 | Timer 1 Control (Hi) | TIM1_CTL_H | ??? | Enable | Reset | ??? | ||||
$32 | Timer 1 Preset (Lo) | TIM1_PRE_L | Preset | |||||||
$33 | Timer 1 Preset (Hi) | TIM1_PRE_H | Preset | |||||||
$34 | Timer 1 Pivot (Lo) | TIM1_PVT_L | Pivot | |||||||
$35 | Timer 1 Pivot (Hi) | TIM1_PVT_H | Pivot | |||||||
$36 | Timer 1 Count (Lo) | TIM1_CNT_L | Count | |||||||
$37 | Timer 1 Count (Hi) | TIM1_CNT_H | Count | |||||||
$38 | Timer 2 Control (Lo) | TIM2_CTL_L | 16-bit Mode | ??? | Enable | Reset | ??? | |||
$39 | Timer 2 Control (HI) | TIM2_CTL_H | ??? | Enable | Reset | ??? | ||||
$3A | Timer 2 Preset (Lo) | TIM2_PRE_L | Preset | |||||||
$3B | Timer 2 Preset (Hi) | TIM2_PRE_H | Preset | |||||||
$3C | Timer 2 Pivot (Lo) | TIM2_PVT_L | Pivot | |||||||
$3D | Timer 2 Pivot (Hi) | TIM2_PVT_H | Pivot | |||||||
$3E | Timer 2 Count (Lo) | TIM2_CNT_L | Count | |||||||
$3F | Timer 2 Count (Hi) | TIM2_CNT_H | Count | |||||||
$40 | 256Hz Timer Control | TIM256_CTRL | Reset | Enable | ||||||
$41 | 256Hz Timer Counter | TIM256_CNT | Count | |||||||
$44 | ||||||||||
$45 | ||||||||||
$46 | ||||||||||
$47 | ||||||||||
$48 | Timer 3 Control (Lo) | TIM3_CTL_L | 16-bit Mode | ??? | Enable | Reset | ??? | |||
$49 | Timer 3 Control (Hi) | TIM3_CTL_H | ??? | Enable | Reset | ??? | ||||
$4A | Timer 3 Preset (Lo) | TIM3_PRE_L | Preset | |||||||
$4B | Timer 3 Preset (Hi) | TIM3_PRE_H | Preset | |||||||
$4C | Timer 3 Pivot (Lo) | TIM3_PVT_L | Pivot | |||||||
$4D | Timer 3 Pivot (Hi) | TIM3_PVT_H | Pivot | |||||||
$4E | Timer 3 Count (Lo) | TIM3_CNT_L | Count | |||||||
$4F | Timer 3 Count (Hi) | TIM3_CNT_H | Count | |||||||
$50 | ||||||||||
$51 | ||||||||||
$52 | Key-Pad Status (Active 0) | KEY_PAD | Power | Right | Left | Down | Up | C | B | A |
$53 | ||||||||||
$54 | ||||||||||
$55 | ||||||||||
$60 | I/O Direction Select | IO_DIR | ?? | ?? | IR Rx Disable | Rumble | EEPROM Clock | EEPROM Data | IR Rx | IR Tx |
$61 | I/O Data Register | IO_DATA | ?? | ?? | IR Rx Disable | Rumble | EEPROM Clock | EEPROM Data | IR Rx | IR Tx |
$62 | ||||||||||
$70 | ??? (Mutes audio if lower 2 bits != 0) | ?? | ?? | ?? | ||||||
$71 | Audio Volume Control | AUD_VOL | ?? | Volume (Mute,50%,50%,100%) | ||||||
$80 | PRC Stage Control | PRC_MODE | Map Size | Ena Copy | Ena Sprites | Ena Map | Invert Map | |||
$81 | PRC Rate Control | PRC_SPEED | Frame counter | Rate divider | ??? | |||||
$82 | PRC Map Tile Base (Lo) | PRC_MAP_LO | Map Tile Base | |||||||
$83 | PRC Map Tile Base (Mid) | PRC_MAP_MID | Map Tile Base | |||||||
$84 | PRC Map Tile Base (Hi) | PRC_MAP_HI | Map Tile Base | |||||||
$85 | PRC Map Vertical Scroll | PRC_SCROLL_Y | Map Scroll Y | |||||||
$86 | PRC Map Horizontal Scroll | PRC_SCROLL_X | Map Scroll X | |||||||
$87 | PRC Sprite Tile Base (Lo) | PRC_SPR_LO | Sprite Tile Base | |||||||
$88 | PRC Sprite Tile Base (Mid) | PRC_SPR_MID | Sprite Tile Base | |||||||
$89 | PRC Sprite Tile Base (Hi) | PRC_SPR_HI | Sprite Tile Base | |||||||
$8A | PRC Counter | PRC_CNT | Count | |||||||
$8B | Unknown (returns 0) | |||||||||
$8C | Unknown (returns 0) | |||||||||
$8D | Unknown (returns 0) | |||||||||
$8E | Unknown (returns 0) | |||||||||
$8F | Unknown (returns 0) | |||||||||
$F0 | Unknown (returns 0) | |||||||||
$F1 | Unknown (returns 0) | |||||||||
$F2 | Unknown (returns 0) | |||||||||
$F3 | Unknown (returns 0) | |||||||||
$F4 | Unknown (returns 0) | |||||||||
$F5 | Unknown (returns 0) | |||||||||
$F6 | Unknown (returns 0) | |||||||||
$F7 | Unknown (returns 0) | |||||||||
$FE | LCD Raw Control Byte | LCD_CTRL | LCD Control I/O | |||||||
$FF | LCD Raw Data Byte | LCD_DATA | LCD Data I/O |