Difference between revisions of "256Hz Timer"
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When $41 overflows the 1 Hz IRQ $0E is fired.<br> | When $41 overflows the 1 Hz IRQ $0E is fired.<br> | ||
| − | When $41 bit 7 | + | When $41 bit 8 increments (overflow from bit 7) (or from 1 to 0 ????) the 2 Hz IRQ $0D is fired.<br> |
| − | When $41 bit 5 | + | When $41 bit 6 increments (overflow from bit 5) the 8 Hz IRQ $0C is fired.<br> |
| − | When $41 bit 3 | + | When $41 bit 4 increments (overflow from bit 3) the 32 Hz IRQ $0B is fired.<br> |
Revision as of 21:42, 29 May 2008
Operation
The 256Hz Timer is enabled by writing the LSB of $40 to 1. This activates the timer. It might be a good idea to also reset the timer by writing the 2nd bit to 1 also.
When the timer is active register $41 is incremented 256 times a second. Since it's an 8 bit register counting from 0 to 255 it overflows exactly 1 time a second.
IRQs tied to 256 Hz timer
The counter register $41 is also used to fire some interrupts at frequencies derived from the 256 Hz clock:
When $41 overflows the 1 Hz IRQ $0E is fired.
When $41 bit 8 increments (overflow from bit 7) (or from 1 to 0 ????) the 2 Hz IRQ $0D is fired.
When $41 bit 6 increments (overflow from bit 5) the 8 Hz IRQ $0C is fired.
When $41 bit 4 increments (overflow from bit 3) the 32 Hz IRQ $0B is fired.
