Difference between revisions of "PM Pinouts"

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(New page: == Cartridge Pinouts == {| border="1" style="text-align:left" !Conn. !Card !TSOP !Name !Direction !Function |- |1 |B1 |note 1 |VCC |. |Power supply. |- |2 |B1.5 |note 1 |VCC |. |Power sup...)
 
Line 6: Line 6:
 
!TSOP
 
!TSOP
 
!Name
 
!Name
!Direction
+
!Direction (Rel: System)
 
!Function
 
!Function
 
|-
 
|-
Line 27: Line 27:
 
|2
 
|2
 
|A20
 
|A20
|<=
+
|OUT
 
|Address bit 20.
 
|Address bit 20.
 
|-
 
|-
Line 34: Line 34:
 
|3
 
|3
 
|A9/A19
 
|A9/A19
|<=
+
|OUT
 
|Address bit 9 is latched when LALH is high. Address bit 19 is latched when HALH is high.
 
|Address bit 9 is latched when LALH is high. Address bit 19 is latched when HALH is high.
 
|-
 
|-
Line 41: Line 41:
 
|4
 
|4
 
|A8/A18
 
|A8/A18
|<=
+
|OUT
 
|Address bit 8 is latched when LALH is high. Address bit 18 is latched when HALH is high.
 
|Address bit 8 is latched when LALH is high. Address bit 18 is latched when HALH is high.
 
|-
 
|-
Line 48: Line 48:
 
|5
 
|5
 
|A7/A17
 
|A7/A17
|<=
+
|OUT
 
|Address bit 7 is latched when LALH is high. Address bit 17 is latched when HALH is high.
 
|Address bit 7 is latched when LALH is high. Address bit 17 is latched when HALH is high.
 
|-
 
|-
Line 55: Line 55:
 
|6
 
|6
 
|A6/A16
 
|A6/A16
|<=
+
|OUT
 
|Address bit 6 is latched when LALH is high. Address bit 16 is latched when HALH is high.
 
|Address bit 6 is latched when LALH is high. Address bit 16 is latched when HALH is high.
 
|-
 
|-
Line 62: Line 62:
 
|7
 
|7
 
|A5/A15
 
|A5/A15
|<=
+
|OUT
 
|Address bit 5 is latched when LALH is high. Address bit 15 is latched when HALH is high.
 
|Address bit 5 is latched when LALH is high. Address bit 15 is latched when HALH is high.
 
|-
 
|-
Line 69: Line 69:
 
|8
 
|8
 
|A4/A14
 
|A4/A14
|<=
+
|OUT
 
|Address bit 4 is latched when LALH is high. Address bit 14 is latched when HALH is high.
 
|Address bit 4 is latched when LALH is high. Address bit 14 is latched when HALH is high.
 
|-
 
|-
Line 76: Line 76:
 
|9
 
|9
 
|A3/A13
 
|A3/A13
|<=
+
|OUT
 
|Address bit 3 is latched when LALH is high. Address bit 13 is latched when HALH is high.
 
|Address bit 3 is latched when LALH is high. Address bit 13 is latched when HALH is high.
 
|-
 
|-
Line 83: Line 83:
 
|10
 
|10
 
|A2/A12
 
|A2/A12
|<=
+
|OUT
 
|Address bit 2 is latched when LALH is high. Address bit 12 is latched when HALH is high.
 
|Address bit 2 is latched when LALH is high. Address bit 12 is latched when HALH is high.
 
|-
 
|-
Line 90: Line 90:
 
|11
 
|11
 
|A1/A11
 
|A1/A11
|<=
+
|OUT
 
|Address bit 1 is latched when LALH is high. Address bit 11 is latched when HALH is high.
 
|Address bit 1 is latched when LALH is high. Address bit 11 is latched when HALH is high.
 
|-
 
|-
Line 97: Line 97:
 
|12
 
|12
 
|A0/A10
 
|A0/A10
|<=
+
|OUT
 
|Address bit 0 is latched when LALH is high. Address bit 10 is latched when HALH is high.
 
|Address bit 0 is latched when LALH is high. Address bit 10 is latched when HALH is high.
 
|-
 
|-
Line 111: Line 111:
 
|14
 
|14
 
|HALE
 
|HALE
|<=
+
|OUT
 
|High address bits are latched when HALE is high.
 
|High address bits are latched when HALE is high.
 
|-
 
|-
Line 125: Line 125:
 
|15
 
|15
 
|LALE
 
|LALE
|<=
+
|OUT
 
|Low address bits are latched when LALE is high.
 
|Low address bits are latched when LALE is high.
 
|-
 
|-
Line 139: Line 139:
 
|31
 
|31
 
|D0
 
|D0
|<=>
+
|BIDIR
 
|Data bit 0 is output when OE is high.
 
|Data bit 0 is output when OE is high.
 
|-
 
|-
Line 146: Line 146:
 
|30
 
|30
 
|D1
 
|D1
|<=>
+
|BIDIR
 
|Data bit 1 is output when OE is high.
 
|Data bit 1 is output when OE is high.
 
|-
 
|-
Line 153: Line 153:
 
|29
 
|29
 
|D2
 
|D2
|<=>
+
|BIDIR
 
|Data bit 2 is output when OE is high.
 
|Data bit 2 is output when OE is high.
 
|-
 
|-
Line 160: Line 160:
 
|27
 
|27
 
|D3
 
|D3
|<=>
+
|BIDIR
 
|Data bit 3 is output when OE is high.
 
|Data bit 3 is output when OE is high.
 
|-
 
|-
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|26
 
|26
 
|D4
 
|D4
|<=>
+
|BIDIR
 
|Data bit 4 is output when OE is high.
 
|Data bit 4 is output when OE is high.
 
|-
 
|-
Line 174: Line 174:
 
|25
 
|25
 
|D5
 
|D5
|<=>
+
|BIDIR
 
|Data bit 5 is output when OE is high.
 
|Data bit 5 is output when OE is high.
 
|-
 
|-
Line 181: Line 181:
 
|23
 
|23
 
|D6
 
|D6
|<=>
+
|BIDIR
 
|Data bit 6 is output when OE is high.
 
|Data bit 6 is output when OE is high.
 
|-
 
|-
Line 188: Line 188:
 
|22
 
|22
 
|D7
 
|D7
|<=>
+
|BIDIR
 
|Data bit 7 is output when OE is high.
 
|Data bit 7 is output when OE is high.
 
|-
 
|-
Line 195: Line 195:
 
|20
 
|20
 
|OE
 
|OE
|<=
+
|OUT
 
|Output Enable. Data bits are output when OE is high.
 
|Output Enable. Data bits are output when OE is high.
 
|-
 
|-
Line 202: Line 202:
 
|.
 
|.
 
|IRQ
 
|IRQ
|=>
+
|IN
 
|Cause "Cartridge IRQ" interrupt when IRQ go high.
 
|Cause "Cartridge IRQ" interrupt when IRQ go high.
 
|-
 
|-
Line 209: Line 209:
 
|19
 
|19
 
|WE
 
|WE
|<=
+
|OUT
 
|Write Enable. Pulled down with 100K in cartridge.
 
|Write Enable. Pulled down with 100K in cartridge.
 
|-
 
|-
Line 216: Line 216:
 
|18
 
|18
 
|CS
 
|CS
|<=
+
|OUT
 
|Chip select. Enables chip control. Pulled down with 100K in cartridge.
 
|Chip select. Enables chip control. Pulled down with 100K in cartridge.
 
|-
 
|-
Line 223: Line 223:
 
|.
 
|.
 
|CARD_N
 
|CARD_N
|=>
+
|IN
 
|Card detect. Active-low. It is connected to GND in the cartridge.
 
|Card detect. Active-low. It is connected to GND in the cartridge.
 
|-
 
|-

Revision as of 17:44, 21 May 2008

Cartridge Pinouts

Conn. Card TSOP Name Direction (Rel: System) Function
1 B1 note 1 VCC . Power supply.
2 B1.5 note 1 VCC . Power supply.
3 B2 2 A20 OUT Address bit 20.
4 B2.5 3 A9/A19 OUT Address bit 9 is latched when LALH is high. Address bit 19 is latched when HALH is high.
5 B3 4 A8/A18 OUT Address bit 8 is latched when LALH is high. Address bit 18 is latched when HALH is high.
6 B3.5 5 A7/A17 OUT Address bit 7 is latched when LALH is high. Address bit 17 is latched when HALH is high.
7 B4 6 A6/A16 OUT Address bit 6 is latched when LALH is high. Address bit 16 is latched when HALH is high.
8 B4.5 7 A5/A15 OUT Address bit 5 is latched when LALH is high. Address bit 15 is latched when HALH is high.
9 B5 8 A4/A14 OUT Address bit 4 is latched when LALH is high. Address bit 14 is latched when HALH is high.
10 B5.5 9 A3/A13 OUT Address bit 3 is latched when LALH is high. Address bit 13 is latched when HALH is high.
11 B6 10 A2/A12 OUT Address bit 2 is latched when LALH is high. Address bit 12 is latched when HALH is high.
12 B6.5 11 A1/A11 OUT Address bit 1 is latched when LALH is high. Address bit 11 is latched when HALH is high.
13 B7 12 A0/A10 OUT Address bit 0 is latched when LALH is high. Address bit 10 is latched when HALH is high.
14 B7.5 note 1 VCC . Power supply.
15 B8 14 HALE OUT High address bits are latched when HALE is high.
16 . . . . No pad on cartridge.
17 B9/M1 15 LALE OUT Low address bits are latched when LALE is high.
18 B9.5 note 2 GND . Ground.
19 B10 31 D0 BIDIR Data bit 0 is output when OE is high.
20 B10.5 30 D1 BIDIR Data bit 1 is output when OE is high.
21 B11 29 D2 BIDIR Data bit 2 is output when OE is high.
22 B11.5 27 D3 BIDIR Data bit 3 is output when OE is high.
23 B12 26 D4 BIDIR Data bit 4 is output when OE is high.
24 B12.5 25 D5 BIDIR Data bit 5 is output when OE is high.
25 B13 23 D6 BIDIR Data bit 6 is output when OE is high.
26 B13.5 22 D7 BIDIR Data bit 7 is output when OE is high.
27 B14 20 OE OUT Output Enable. Data bits are output when OE is high.
28 B14.5 . IRQ IN Cause "Cartridge IRQ" interrupt when IRQ go high.
29 B15 19 WE OUT Write Enable. Pulled down with 100K in cartridge.
30 B15.5 18 CS OUT Chip select. Enables chip control. Pulled down with 100K in cartridge.
31 B16 . CARD_N IN Card detect. Active-low. It is connected to GND in the cartridge.
32 B16.5 note 2 GND . Ground.
33 B17 note 2 GND . Ground.

note 1: VCC on pin 1,21,28,32. LVTTL.

note 2: GND on pin 13,16,17,24.

Abbreviations

PM = Pokémon Mini

TSOP = Thin Small Outline Package

LVTTL = Low Voltage Transistor-Transistor Level (3.3 Volt)

ROM = Read Only Memory

ALH = Address Latch High

OE = Output Enable

A? = Address signal

CS? = Chip Select

VCC = Power supply

GND = Signal ground

TSOP Chip

   MX23L4004    TSOP package
.-------------/ /-------------.
|  1 VCC               VCC 32 |
|  2 A20               D0  31 |
|  3 A9/A19            D1  30 |
|  4 A8/A18            D2  29 |
|  5 A7/A17            VCC 28 |
|  6 A6/A16            D3  27 |
|  7 A5/A15            D4  26 |
|  8 A4/A14            D5  25 |
|  9 A3/A13            GND 24 |
| 10 A2/A12            D6  23 |
| 11 A1/A11            D7  22 |
| 12 A0/A10            VCC 21 |
| 13 GND               OE  20 |
| 14 HALE              WE  19 |
| 15 LALE              CS  18 |
| 16 GND               GND 17 |
`-------------/ /-------------'

PCB silk screen text

"MIN-KCM1-01"

"4M MASKROM" (4 Mbit)

Pads B1 to B17 are labeled.

IC U1

"MX23L4004-12A" (Macronix)

"MIN-MPBE-0 E" (Mini PinBall)

TSOP