Difference between revisions of "PM Registers"

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m (Register Mapping)
(Register Mapping)
Line 77: Line 77:
 
| $18
 
| $18
 
| Timer 1 Prescalars
 
| Timer 1 Prescalars
| TIM1_SCALE
+
| TIM_SCALE1
 
| style="background-color:#80FF80;"| Enable Hi
 
| style="background-color:#80FF80;"| Enable Hi
 
| colspan="3" style="background-color:#80FF80;"| Hi Scalar
 
| colspan="3" style="background-color:#80FF80;"| Hi Scalar
Line 85: Line 85:
 
| $19
 
| $19
 
| Timer Type Enables \ Timer 1 Speeds
 
| Timer Type Enables \ Timer 1 Speeds
| TIM1_SPEED_ENA
+
| TIM_ENA_SPEED1
 
| colspan="2" style="border:none;background-color:#808080;"|
 
| colspan="2" style="border:none;background-color:#808080;"|
 
| style="background-color:#80FF80;"| Enable Fast
 
| style="background-color:#80FF80;"| Enable Fast
Line 95: Line 95:
 
| $1A
 
| $1A
 
| Timer 2 Prescalars
 
| Timer 2 Prescalars
| TIM2_SCALE
+
| TIM_SCALE2
 
| style="background-color:#80FF80;"| Enable Hi
 
| style="background-color:#80FF80;"| Enable Hi
 
| colspan="3" style="background-color:#80FF80;"| Hi Scalar
 
| colspan="3" style="background-color:#80FF80;"| Hi Scalar
Line 103: Line 103:
 
| $1B
 
| $1B
 
| Timer 2 Speeds
 
| Timer 2 Speeds
| TIM2_SPEED
+
| TIM_SPEED2
 
| colspan="6" style="border:none;background-color:#808080;"|
 
| colspan="6" style="border:none;background-color:#808080;"|
 
| style="background-color:#80FF80;"| Slow (Hi)
 
| style="background-color:#80FF80;"| Slow (Hi)
Line 110: Line 110:
 
| $1C
 
| $1C
 
| Timer 3 Prescalars
 
| Timer 3 Prescalars
| TIM3_SCALE
+
| TIM_SCALE3
 
| style="background-color:#80FF80;"| Enable Hi
 
| style="background-color:#80FF80;"| Enable Hi
 
| colspan="3" style="background-color:#80FF80;"| Hi Scalar
 
| colspan="3" style="background-color:#80FF80;"| Hi Scalar
Line 118: Line 118:
 
| $1D
 
| $1D
 
| Timer 3 Speeds
 
| Timer 3 Speeds
| TIM3_SPEED
+
| TIM_SPEED3
 
| colspan="6" style="border:none;background-color:#808080;"|
 
| colspan="6" style="border:none;background-color:#808080;"|
 
| style="background-color:#80FF80;"| Slow (Hi)
 
| style="background-color:#80FF80;"| Slow (Hi)
Line 125: Line 125:
 
| $20
 
| $20
 
| [[PM_IRQs|IRQ Priority 1]]
 
| [[PM_IRQs|IRQ Priority 1]]
| IRQ_PRI_1
+
| IRQ_PRI1
 
| colspan="2" style="background-color:#80FF80;"| IRQ $03 ~ $04
 
| colspan="2" style="background-color:#80FF80;"| IRQ $03 ~ $04
 
| colspan="2" style="background-color:#80FF80;"| IRQ $05 ~ $06
 
| colspan="2" style="background-color:#80FF80;"| IRQ $05 ~ $06
Line 133: Line 133:
 
| $21
 
| $21
 
| [[PM_IRQs|IRQ Priority 2]]
 
| [[PM_IRQs|IRQ Priority 2]]
| IRQ_PRI_2
+
| IRQ_PRI2
 
| colspan="2" style="background-color:#80FF80;"| IRQ $0B ~ $0E
 
| colspan="2" style="background-color:#80FF80;"| IRQ $0B ~ $0E
 
| colspan="2" style="background-color:#80FF80;"| IRQ $13 ~ $14
 
| colspan="2" style="background-color:#80FF80;"| IRQ $13 ~ $14
Line 141: Line 141:
 
| $22
 
| $22
 
| [[PM_IRQs|IRQ Priority 3]]
 
| [[PM_IRQs|IRQ Priority 3]]
| IRQ_PRI_3
+
| IRQ_PRI3
 
| colspan="6" style="border:none;background-color:#808080;"|
 
| colspan="6" style="border:none;background-color:#808080;"|
 
| colspan="2" style="background-color:#80FF80;"| IRQ $0F~$10
 
| colspan="2" style="background-color:#80FF80;"| IRQ $0F~$10
Line 147: Line 147:
 
| $23
 
| $23
 
| [[PM_IRQs|IRQ Enable 1]]
 
| [[PM_IRQs|IRQ Enable 1]]
| IRQ_ENA_1
+
| IRQ_ENA1
 
| style="background-color:#80FF80;"| IRQ $03
 
| style="background-color:#80FF80;"| IRQ $03
 
| style="background-color:#80FF80;"| IRQ $04
 
| style="background-color:#80FF80;"| IRQ $04
Line 159: Line 159:
 
| $24
 
| $24
 
| [[PM_IRQs|IRQ Enable 2]]
 
| [[PM_IRQs|IRQ Enable 2]]
| IRQ_ENA_2
+
| IRQ_ENA2
 
| colspan="2" style="border:none;background-color:#808080;"|
 
| colspan="2" style="border:none;background-color:#808080;"|
 
| style="background-color:#80FF80;"| IRQ $0B
 
| style="background-color:#80FF80;"| IRQ $0B
Line 170: Line 170:
 
| $25
 
| $25
 
| [[PM_IRQs|IRQ Enable 3]]
 
| [[PM_IRQs|IRQ Enable 3]]
| IRQ_ENA_3
+
| IRQ_ENA3
 
| style="background-color:#80FF80;"| IRQ $15
 
| style="background-color:#80FF80;"| IRQ $15
 
| style="background-color:#80FF80;"| IRQ $16
 
| style="background-color:#80FF80;"| IRQ $16
Line 182: Line 182:
 
| $26
 
| $26
 
| [[PM_IRQs|IRQ Enable 4]]
 
| [[PM_IRQs|IRQ Enable 4]]
| IRQ_ENA_4
+
| IRQ_ENA4
 
| style="background-color:#80FF80;"| IRQ $0F
 
| style="background-color:#80FF80;"| IRQ $0F
 
| style="background-color:#80FF80;"| IRQ $10
 
| style="background-color:#80FF80;"| IRQ $10
Line 194: Line 194:
 
| $27
 
| $27
 
| [[PM_IRQs|IRQ Active 1]]
 
| [[PM_IRQs|IRQ Active 1]]
| IRQ_ACT_1
+
| IRQ_ACT1
 
| style="background-color:#FFCC00;"| IRQ $03
 
| style="background-color:#FFCC00;"| IRQ $03
 
| style="background-color:#FFCC00;"| IRQ $04
 
| style="background-color:#FFCC00;"| IRQ $04
Line 206: Line 206:
 
| $28
 
| $28
 
| [[PM_IRQs|IRQ Active 2]]
 
| [[PM_IRQs|IRQ Active 2]]
| IRQ_ACT_2
+
| IRQ_ACT2
 
| colspan="2" style="border:none;background-color:#808080;"|
 
| colspan="2" style="border:none;background-color:#808080;"|
 
| style="background-color:#FFCC00;"| IRQ $0B
 
| style="background-color:#FFCC00;"| IRQ $0B
Line 217: Line 217:
 
| $29
 
| $29
 
| [[PM_IRQs|IRQ Active 3]]
 
| [[PM_IRQs|IRQ Active 3]]
| IRQ_ACT_3
+
| IRQ_ACT3
 
| style="background-color:#FFCC00;"| IRQ $15
 
| style="background-color:#FFCC00;"| IRQ $15
 
| style="background-color:#FFCC00;"| IRQ $16
 
| style="background-color:#FFCC00;"| IRQ $16
Line 229: Line 229:
 
| $2A
 
| $2A
 
| [[PM_IRQs|IRQ Active 4]]
 
| [[PM_IRQs|IRQ Active 4]]
| IRQ_ACT_4
+
| IRQ_ACT4
 
| style="background-color:#FFCC00;"| IRQ $0F
 
| style="background-color:#FFCC00;"| IRQ $0F
 
| style="background-color:#FFCC00;"| IRQ $10
 
| style="background-color:#FFCC00;"| IRQ $10
Line 241: Line 241:
 
| $30
 
| $30
 
| Timer 1 Control (Lo)
 
| Timer 1 Control (Lo)
| TIM1_CTL_L
+
| TIM_CTL1_L
 
| style="background-color:#80FF80;"| 16-bit Mode
 
| style="background-color:#80FF80;"| 16-bit Mode
 
| colspan="3" style="border:none;background-color:#808080;"|
 
| colspan="3" style="border:none;background-color:#808080;"|
Line 251: Line 251:
 
| $31
 
| $31
 
| Timer 1 Control (Hi)
 
| Timer 1 Control (Hi)
| TIM1_CTL_H
+
| TIM_CTL1_H
 
| colspan="4" style="border:none;background-color:#808080;"|
 
| colspan="4" style="border:none;background-color:#808080;"|
 
| style="background-color:#80FF80;"| ???
 
| style="background-color:#80FF80;"| ???
Line 260: Line 260:
 
| $32
 
| $32
 
| Timer 1 Preset (Lo)
 
| Timer 1 Preset (Lo)
| TIM1_PRE_L
+
| TIM_PRE1_L
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
|-
 
|-
 
| $33
 
| $33
 
| Timer 1 Preset (Hi)
 
| Timer 1 Preset (Hi)
| TIM1_PRE_H
+
| TIM_PRE1_H
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
|-
 
|-
 
| $34
 
| $34
 
| Timer 1 Pivot (Lo)
 
| Timer 1 Pivot (Lo)
| TIM1_PVT_L
+
| TIM_PVT1_L
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
|-
 
|-
 
| $35
 
| $35
 
| Timer 1 Pivot (Hi)
 
| Timer 1 Pivot (Hi)
| TIM1_PVT_H
+
| TIM_PVT1_H
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
|-
 
|-
 
| $36
 
| $36
 
| Timer 1 Count (Lo)
 
| Timer 1 Count (Lo)
| TIM1_CNT_L
+
| TIM_CNT1_L
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
|-
 
|-
 
| $37
 
| $37
 
| Timer 1 Count (Hi)
 
| Timer 1 Count (Hi)
| TIM1_CNT_H
+
| TIM_CNT1_H
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
|-
 
|-
 
| $38
 
| $38
 
| Timer 2 Control (Lo)
 
| Timer 2 Control (Lo)
| TIM2_CTL_L
+
| TIM_CTL2_L
 
| style="background-color:#80FF80;"| 16-bit Mode
 
| style="background-color:#80FF80;"| 16-bit Mode
 
| colspan="3" style="border:none;background-color:#808080;"|
 
| colspan="3" style="border:none;background-color:#808080;"|
Line 300: Line 300:
 
| $39
 
| $39
 
| Timer 2 Control (HI)
 
| Timer 2 Control (HI)
| TIM2_CTL_H
+
| TIM_CTL2_H
 
| colspan="4" style="border:none;background-color:#808080;"|
 
| colspan="4" style="border:none;background-color:#808080;"|
 
| style="background-color:#80FF80;"| ???
 
| style="background-color:#80FF80;"| ???
 
| style="background-color:#80FF80;"| Enable
 
| style="background-color:#80FF80;"| Enable
|style="background-color:#FFFF00;"| Reset
+
| style="background-color:#FFFF00;"| Reset
 
| style="background-color:#80FF80;"| ???
 
| style="background-color:#80FF80;"| ???
 
|-
 
|-
 
| $3A
 
| $3A
 
| Timer 2 Preset (Lo)
 
| Timer 2 Preset (Lo)
| TIM2_PRE_L
+
| TIM_PRE2_L
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
|-
 
|-
 
| $3B
 
| $3B
 
| Timer 2 Preset (Hi)
 
| Timer 2 Preset (Hi)
| TIM2_PRE_H
+
| TIM_PRE2_H
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
|-
 
|-
 
| $3C
 
| $3C
 
| Timer 2 Pivot (Lo)
 
| Timer 2 Pivot (Lo)
| TIM2_PVT_L
+
| TIM_PVT2_L
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
|-
 
|-
 
| $3D
 
| $3D
 
| Timer 2 Pivot (Hi)
 
| Timer 2 Pivot (Hi)
| TIM2_PVT_H
+
| TIM_PVT2_H
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
|-
 
|-
 
| $3E
 
| $3E
 
| Timer 2 Count (Lo)
 
| Timer 2 Count (Lo)
| TIM2_CNT_L
+
| TIM_CNT2_L
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
|-
 
|-
 
| $3F
 
| $3F
 
| Timer 2 Count (Hi)
 
| Timer 2 Count (Hi)
| TIM2_CNT_H
+
| TIM_CNT2_H
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
|-
 
|-
Line 359: Line 359:
 
| $48
 
| $48
 
| Timer 3 Control (Lo)
 
| Timer 3 Control (Lo)
| TIM3_CTL_L
+
| TIM_CTL3_L
 
| style="background-color:#80FF80;"| 16-bit Mode
 
| style="background-color:#80FF80;"| 16-bit Mode
 
| colspan="3" style="border:none;background-color:#808080;"|
 
| colspan="3" style="border:none;background-color:#808080;"|
Line 369: Line 369:
 
| $49
 
| $49
 
| Timer 3 Control (Hi)
 
| Timer 3 Control (Hi)
| TIM3_CTL_H
+
| TIM_CTL3_H
 
| colspan="4" style="border:none;background-color:#808080;"|
 
| colspan="4" style="border:none;background-color:#808080;"|
 
| style="background-color:#80FF80;"| ???
 
| style="background-color:#80FF80;"| ???
Line 378: Line 378:
 
| $4A
 
| $4A
 
| Timer 3 Preset (Lo)
 
| Timer 3 Preset (Lo)
| TIM3_PRE_L
+
| TIM_PRE3_L
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
|-
 
|-
 
| $4B
 
| $4B
 
| Timer 3 Preset (Hi)
 
| Timer 3 Preset (Hi)
| TIM3_PRE_H
+
| TIM_PRE3_H
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
| colspan="8" style="background-color:#80FF80;"| Preset
 
|-
 
|-
 
| $4C
 
| $4C
 
| Timer 3 Pivot (Lo)
 
| Timer 3 Pivot (Lo)
| TIM3_PVT_L
+
| TIM_PVT3_L
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
|-
 
|-
 
| $4D
 
| $4D
 
| Timer 3 Pivot (Hi)
 
| Timer 3 Pivot (Hi)
| TIM3_PVT_H
+
| TIM_PVT3_H
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
| colspan="8" style="background-color:#80FF80;"| Pivot
 
|-
 
|-
 
| $4E
 
| $4E
 
| Timer 3 Count (Lo)
 
| Timer 3 Count (Lo)
| TIM3_CNT_L
+
| TIM_CNT3_L
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
|-
 
|-
 
| $4F
 
| $4F
 
| Timer 3 Count (Hi)
 
| Timer 3 Count (Hi)
| TIM3_CNT_H
+
| TIM_CNT3_H
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
| colspan="8" style="background-color:#00FFFF;"| Count
 
|-
 
|-

Revision as of 21:32, 26 May 2008

Register Overview

The Pokemon Mini maps $2000 ~ $20FF as hardware control registers. This area is reserved for hardware related functions such as video, audio, general purpose timers, hardware I/O and system control.

Much of this address space is mapped as Open-Bus, leading us to beleive that this area is not used for any purpose. Other areas respond to requests but their purpose is yet undetermined.

Registers tend to be controlled on a bit level, so for the sanity purposes, they will be broken down to this level. At any point they are shown spanning multiple columns, that indicates that it is a multi-bit value and should be treated as if they were a number.

The bits themselves come in four flavors: Read-only, Write-Only, Read-Write, and S-R Strobe. Write-Only registers typically return a zero value, and are generally only used for things such as resetting timers. S-R Strobes are used for clearing interrupt events. Writting a logical '1' to any bit that is set will result in a bit being cleared, where as '0' leaves them unchanged.

Any register not included on this list reads as Open-Bus and will be excluded unless a function has otherwise been determined.

Register Mapping

Register Map Legend
Unused Read/Write Read Only Write Only S-R Strobe
Address Register Const Name 7 6 5 4 3 2 1 0
$00 System Control 1 SYS_CTL1 Startup Contrast  ???  ???
$01
$02
$08 Second Counter Control SEC_CTRL Reset Enable
$09 Second Counter Lo SEC_CNT_LO Counter
$0A Second Counter Med SEC_CNT_MED Counter
$0B Second Counter Hi SEC_CNT_HI Counter
$10 Battery Sensor SYS_BATT Low Battery  ?? (Low-Level?)
$18 Timer 1 Prescalars TIM_SCALE1 Enable Hi Hi Scalar Enable Low Low Scalar
$19 Timer Type Enables \ Timer 1 Speeds TIM_ENA_SPEED1 Enable Fast Enable Slow Slow (Hi) Slow (Lo)
$1A Timer 2 Prescalars TIM_SCALE2 Enable Hi Hi Scalar Enable Low Low Scalar
$1B Timer 2 Speeds TIM_SPEED2 Slow (Hi) Slow (Lo)
$1C Timer 3 Prescalars TIM_SCALE3 Enable Hi Hi Scalar Enable Low Low Scalar
$1D Timer 3 Speeds TIM_SPEED3 Slow (Hi) Slow (Lo)
$20 IRQ Priority 1 IRQ_PRI1 IRQ $03 ~ $04 IRQ $05 ~ $06 IRQ $07 ~ $08 IRQ $09 ~ $0A
$21 IRQ Priority 2 IRQ_PRI2 IRQ $0B ~ $0E IRQ $13 ~ $14 IRQ $15 ~ $1C IRQ ?? ($1D ~ $1F?)
$22 IRQ Priority 3 IRQ_PRI3 IRQ $0F~$10
$23 IRQ Enable 1 IRQ_ENA1 IRQ $03 IRQ $04 IRQ $05 IRQ $06 IRQ $07 IRQ $08 IRQ $09 IRQ $0A
$24 IRQ Enable 2 IRQ_ENA2 IRQ $0B IRQ $0C IRQ $0D IRQ $0E IRQ $13 IRQ $14
$25 IRQ Enable 3 IRQ_ENA3 IRQ $15 IRQ $16 IRQ $17 IRQ $18 IRQ $19 IRQ $1A IRQ $1B IRQ $1C
$26 IRQ Enable 4 IRQ_ENA4 IRQ $0F IRQ $10 IRQ ?? IRQ ?? IRQ $1D IRQ $1E IRQ $1F
$27 IRQ Active 1 IRQ_ACT1 IRQ $03 IRQ $04 IRQ $05 IRQ $06 IRQ $07 IRQ $08 IRQ $09 IRQ $0A
$28 IRQ Active 2 IRQ_ACT2 IRQ $0B IRQ $0C IRQ $0D IRQ $0E IRQ $13 IRQ $14
$29 IRQ Active 3 IRQ_ACT3 IRQ $15 IRQ $16 IRQ $17 IRQ $18 IRQ $19 IRQ $1A IRQ $1B IRQ $1C
$2A IRQ Active 4 IRQ_ACT4 IRQ $0F IRQ $10 IRQ ?? IRQ ?? IRQ $1D IRQ $1E IRQ $1F
$30 Timer 1 Control (Lo) TIM_CTL1_L 16-bit Mode  ??? Enable Reset  ???
$31 Timer 1 Control (Hi) TIM_CTL1_H  ??? Enable Reset  ???
$32 Timer 1 Preset (Lo) TIM_PRE1_L Preset
$33 Timer 1 Preset (Hi) TIM_PRE1_H Preset
$34 Timer 1 Pivot (Lo) TIM_PVT1_L Pivot
$35 Timer 1 Pivot (Hi) TIM_PVT1_H Pivot
$36 Timer 1 Count (Lo) TIM_CNT1_L Count
$37 Timer 1 Count (Hi) TIM_CNT1_H Count
$38 Timer 2 Control (Lo) TIM_CTL2_L 16-bit Mode  ??? Enable Reset  ???
$39 Timer 2 Control (HI) TIM_CTL2_H  ??? Enable Reset  ???
$3A Timer 2 Preset (Lo) TIM_PRE2_L Preset
$3B Timer 2 Preset (Hi) TIM_PRE2_H Preset
$3C Timer 2 Pivot (Lo) TIM_PVT2_L Pivot
$3D Timer 2 Pivot (Hi) TIM_PVT2_H Pivot
$3E Timer 2 Count (Lo) TIM_CNT2_L Count
$3F Timer 2 Count (Hi) TIM_CNT2_H Count
$40 256Hz Timer Control TIM256_CTRL Reset Enable
$41 256Hz Timer Counter TIM256_CNT Count
$44
$45
$46
$47
$48 Timer 3 Control (Lo) TIM_CTL3_L 16-bit Mode  ??? Enable Reset  ???
$49 Timer 3 Control (Hi) TIM_CTL3_H  ??? Enable Reset  ???
$4A Timer 3 Preset (Lo) TIM_PRE3_L Preset
$4B Timer 3 Preset (Hi) TIM_PRE3_H Preset
$4C Timer 3 Pivot (Lo) TIM_PVT3_L Pivot
$4D Timer 3 Pivot (Hi) TIM_PVT3_H Pivot
$4E Timer 3 Count (Lo) TIM_CNT3_L Count
$4F Timer 3 Count (Hi) TIM_CNT3_H Count
$50
$51
$52 Key-Pad Status (Active 0) KEY_PAD Power Right Left Down Up C B A
$53
$54
$55
$60 I/O Direction Select IO_DIR  ??  ?? IR Disable Rumble EEPROM Clock EEPROM Data IR Rx IR Tx
$61 I/O Data Register IO_DATA  ??  ?? IR Disable Rumble EEPROM Clock EEPROM Data IR Rx IR Tx
$62
$70  ??? (Mutes audio if lower 2 bits != 0)  ??  ??  ??
$71 Audio Volume Control AUD_VOL  ?? Volume
$80 PRC Stage Control PRC_MODE Map Size Ena Copy Ena Sprites Ena Map Invert Map
$81 PRC Rate Control PRC_SPEED Frame counter Rate divider  ???
$82 PRC Map Tile Base (Lo) PRC_MAP_LO Map Tile Base
$83 PRC Map Tile Base (Mid) PRC_MAP_MID Map Tile Base
$84 PRC Map Tile Base (Hi) PRC_MAP_HI Map Tile Base
$85 PRC Map Vertical Scroll PRC_SCROLL_Y Map Scroll Y
$86 PRC Map Horizontal Scroll PRC_SCROLL_X Map Scroll X
$87 PRC Sprite Tile Base (Lo) PRC_SPR_LO Sprite Tile Base
$88 PRC Sprite Tile Base (Mid) PRC_SPR_MID Sprite Tile Base
$89 PRC Sprite Tile Base (Hi) PRC_SPR_HI Sprite Tile Base
$8A PRC Counter PRC_CNT Count
$8B Unknown (returns 0)
$8C Unknown (returns 0)
$8D Unknown (returns 0)
$8E Unknown (returns 0)
$8F Unknown (returns 0)
$F0 Unknown (returns 0)
$F1 Unknown (returns 0)
$F2 Unknown (returns 0)
$F3 Unknown (returns 0)
$F4 Unknown (returns 0)
$F5 Unknown (returns 0)
$F6 Unknown (returns 0)
$F7 Unknown (returns 0)
$FE LCD Raw Control Byte LCD_CTRL LCD Control I/O
$FF LCD Raw Data Byte LCD_DATA LCD Data I/O