Difference between revisions of "PM Registers"

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(Register Mapping)
(Register Mapping)
Line 82: Line 82:
 
|-
 
|-
 
| $30
 
| $30
 +
| Timer 1 Control (Lo)
 +
| TIM1_CTL_L
 +
| 16-bit Mode
 +
| colspan="3"|
 +
| ???
 +
| Enable
 +
| Reset
 +
| ???
 
|-
 
|-
 
| $31
 
| $31
 +
| Timer 1 Control (Hi)
 +
| TIM1_CTL_H
 +
| colspan="4"|
 +
| ???
 +
| Enable
 +
| Reset
 +
| ???
 
|-
 
|-
 
| $32
 
| $32
Line 116: Line 131:
 
|-
 
|-
 
| $38
 
| $38
 +
| Timer 2 Control (Lo)
 +
| TIM2_CTL_L
 +
| 16-bit Mode
 +
| colspan="3"|
 +
| ???
 +
| Enable
 +
| Reset
 +
| ???
 
|-
 
|-
 
| $39
 
| $39
 +
| Timer 2 Control (HI)
 +
| TIM2_CTL_H
 +
| colspan="4"|
 +
| ???
 +
| Enable
 +
| Reset
 +
| ???
 
|-
 
|-
 
| $3A
 
| $3A
Line 170: Line 200:
 
|-
 
|-
 
| $48
 
| $48
 +
| Timer 3 Control (Lo)
 +
| TIM3_CTL_L
 +
| 16-bit Mode
 +
| colspan="3"|
 +
| ???
 +
| Enable
 +
| Reset
 +
| ???
 
|-
 
|-
 
| $49
 
| $49
 +
| Timer 3 Control (Hi)
 +
| TIM3_CTL_H
 +
| colspan="4"|
 +
| ???
 +
| Enable
 +
| Reset
 +
| ???
 
|-
 
|-
 
| $4A
 
| $4A

Revision as of 18:28, 25 May 2008

Register Overview

The Pokemon Mini maps $2000 ~ $20FF as hardware control registers. This area is reserved for hardware related functions such as video, audio, general purpose timers, hardware I/O and system control.

Much of this address space is mapped as Open-Bus, leading us to beleive that this area is not used for any purpose. Other areas respond to requests but their purpose is yet undetermined.

Registers tend to be controlled on a bit level, so for the sanity purposes, they will be broken down to this level. At any point they are shown spanning multiple columns, that indicates that it is a multi-bit value and should be treated as if they were a number.

The bits themselves come in four flavors: Read-only, Write-Only, Read-Write, and S-R Strobe. Write-Only registers typically return a zero value, and are generally only used for things such as resetting timers. S-R Strobes are used for clearing interrupt events. Writting a logical '1' to any bit that is set will result in a bit being cleared, where as '0' leaves them unchanged.

Any register not included on this list reads as Open-Bus and will be excluded unless a function has otherwise been determined.

Register Mapping

Address Register Const Name 7 6 5 4 3 2 1 0
$00 System Control 1 SYS_CTL1 Startup Contrast Unknown Unknown
$01
$02
$08
$09
$0A
$0B
$10
$18
$19
$1A
$1B
$1C
$1D
$20
$21
$22
$23
$24
$25
$26
$27
$28
$29
$2A
$30 Timer 1 Control (Lo) TIM1_CTL_L 16-bit Mode  ??? Enable Reset  ???
$31 Timer 1 Control (Hi) TIM1_CTL_H  ??? Enable Reset  ???
$32 Timer 1 Preset (Lo) TIM1_PRE_L Preset
$33 Timer 1 Preset (Hi) TIM1_PRE_H Preset
$34 Timer 1 Pivot (Lo) TIM1_PVT_L Pivot
$35 Timer 1 Pivot (Hi) TIM1_PVT_H Pivot
$36 Timer 1 Count (Lo) TIM1_CNT_L Count
$37 Timer 1 Count (Hi) TIM1_CNT_H Count
$38 Timer 2 Control (Lo) TIM2_CTL_L 16-bit Mode  ??? Enable Reset  ???
$39 Timer 2 Control (HI) TIM2_CTL_H  ??? Enable Reset  ???
$3A Timer 2 Preset (Lo) TIM2_PRE_L Preset
$3B Timer 2 Preset (Hi) TIM2_PRE_H Preset
$3C Timer 2 Pivot (Lo) TIM2_PVT_L Pivot
$3D Timer 2 Pivot (Hi) TIM2_PVT_H Pivot
$3E Timer 2 Count (Lo) TIM2_CNT_L Count
$3F Timer 2 Count (Hi) TIM2_CNT_H Count
$40 256Hz Timer Control TIM256_CTRL Reset Enable
$41 256Hz Timer Counter TIM256_CNT Count
$44
$45
$46
$47
$48 Timer 3 Control (Lo) TIM3_CTL_L 16-bit Mode  ??? Enable Reset  ???
$49 Timer 3 Control (Hi) TIM3_CTL_H  ??? Enable Reset  ???
$4A Timer 3 Preset (Lo) TIM3_PRE_L Preset
$4B Timer 3 Preset (Hi) TIM3_PRE_H Preset
$4C Timer 3 Pivot (Lo) TIM3_PVT_L Pivot
$4D Timer 3 Pivot (Hi) TIM3_PVT_H Pivot
$4E Timer 3 Count (Lo) TIM3_CNT_L Count
$4F Timer 3 Count (Hi) TIM3_CNT_H Count
$50
$51
$52 Key-Pad Status (Active 0) KEY_PAD Power Right Left Down Up C B A
$53
$54
$55
$60
$61
$62
$70
$71
$80
$81
$82 PRC Map Tile Base (Lo) PRC_MAP_LO Map Tile Base
$83 PRC Map Tile Base (Mid) PRC_MAP_MID Map Tile Base
$84 PRC Map Tile Base (Hi) PRC_MAP_HI Map Tile Base
$85 PRC Map Vertical Scroll PRC_SCROLL_Y Map Scroll Y
$86 PRC Map Horizontal Scroll PRC_SCROLL_X Map Scroll X
$87 PRC Sprite Tile Base (Lo) PRC_SPR_LO Sprite Tile Base
$88 PRC Sprite Tile Base (Mid) PRC_SPR_MID Sprite Tile Base
$89 PRC Sprite Tile Base (Hi) PRC_SPR_HI Sprite Tile Base
$8A PRC Counter PRC_CNT Count
$8B Unknown (returns 0)
$8C Unknown (returns 0)
$8D Unknown (returns 0)
$8E Unknown (returns 0)
$8F Unknown (returns 0)
$F0 Unknown (returns 0)
$F1 Unknown (returns 0)
$F2 Unknown (returns 0)
$F3 Unknown (returns 0)
$F4 Unknown (returns 0)
$F5 Unknown (returns 0)
$F6 Unknown (returns 0)
$F7 Unknown (returns 0)
$FE LCD Raw Control Byte LCD_CTRL LCD Control I/O
$FF LCD Raw Data Byte LCD_DATA LCD Data I/O