The Pokemon Mini CPU (Coined the Minx by Team Pokeme) is a microcontroller designed by Nintendo R&D3 for the Pokemon Mini. The processor is 8-bit with 16-bit operations, with instructions created especially for mathematical performance. The processor provides numerous addressing modes with a 24bit addressing bus (with only 21bits mapped externally)
The CPU is clocked at 4.00mhz, although the processor operates on a 4 cycle data access period, leaving the system with a theoretical limit of 1MIPS.
Minx Register Mapping
The Minx operates with a handful of registers. The CPU is an amalgamation of Z80 like paradigms combined with an 8-bit microcontroller like bank system.
Since the program cursor is only 16 bits, it uses a special "delayed" register to account for the upper 8 bits of program access space. When PC has it's most significant bit set, the register V takes the place of the upper 8 bits, extending PC out to 23 bits in total. To prevent bank switch problems, V is "delayed" by the means of register U. After each branch instruction, the value of U is copied to register V implicitly, allowing for full 23bit jumps without special programming tricks or special functions.
The Minx also provides additional facilities to access 24bit addresses using registers. X and Y both provide 24bit addresses using the Xi and Yi register as their upper 8 bits.
Flag and Exception Register
|4||Binary Coded Decimal Mode (8-bit add\sub)||Division By Zero|
|5||Low-Mask Mode (8-bit add\sub)||(Enable Exceptions \ Game cube emulator only)|
While the F register can, in some cases, be treated as a general purpose 8-bit register, the exception register however is not directly accessible by any conventional means. It is also to be noted that the exception trapping needs to be "enabled" by some means we've not discovered yet. Division by zero causes the system to hard lock, and the existence of this register is only known through the reverse engineering of Pokemon Channel's internal emulator. The lower 4 bits of both registers are used for branch conditions and carry chaining for arithmetic. The upper 4 bits are "control" registers.
The I register
Unlike X and Y, the upper 8 bits of the remaining addressing modes are not unique. The register I provides a bank extension to the these remaining 24 bit accesses: [HL], [I+$nnnn], and [N+$nn]. It is generally good practice to maintain I as $00 unless otherwise necessary.
The N indexed mode
The N Indexed mode is most useful for accessing register memory quickly. N provides the mid byte of a 24 bit addressing mode, and the $nn is an 8-bit immediate. In example. [N+$8A] would point to $208A (VPU_CNT) if N = $20 and I = $00. It is rare to see N with any value other than $20, but it is not entirely out of the question to see it change.