Difference between revisions of "S1C88 InstructionSet"
m |
(Reorganized list) |
||
Line 1: | Line 1: | ||
+ | = Move = | ||
+ | |||
== NOP = No Operation == | == NOP = No Operation == | ||
Line 883: | Line 885: | ||
'''Flags Affected:''' None | '''Flags Affected:''' None | ||
+ | |||
+ | = Arithmetic = | ||
== ADD = Addition == | == ADD = Addition == | ||
Line 1,193: | Line 1,197: | ||
== ADC = Addition with Carry == | == ADC = Addition with Carry == | ||
− | |||
[[PM_Opc_ADC8|8 Bit Opcode overview]] | [[PM_Opc_ADC8|8 Bit Opcode overview]] | ||
Line 1,311: | Line 1,314: | ||
'''Flags Affected:''' All | '''Flags Affected:''' All | ||
− | == SBC = Subtraction with Carry == | + | == SBC = Subtraction with Carry == |
− | |||
[[PM_Opc_SBC8|8 Bit Opcode overview]] | [[PM_Opc_SBC8|8 Bit Opcode overview]] | ||
Line 1,584: | Line 1,586: | ||
'''Flags Affected:''' All | '''Flags Affected:''' All | ||
− | == | + | == INC = Increase Register by 1 == |
+ | |||
+ | [[PM_Opc_INC8|8 Bit Opcode overview]] | ||
+ | |||
+ | [[PM_Opc_INC16|16 Bit Opcode overview]] | ||
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 1,591: | Line 1,597: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |80 |
− | |[[ | + | |[[PM_Opc_INC8|INC A]] |
+ | |8 | ||
+ | |- | ||
+ | |81 | ||
+ | |[[PM_Opc_INC8|INC B]] | ||
|8 | |8 | ||
|- | |- | ||
− | | | + | |82 |
− | |[[ | + | |[[PM_Opc_INC8|INC L]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |83 |
− | |[[ | + | |[[PM_Opc_INC8|INC H]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |84 |
− | |[[ | + | |[[PM_Opc_INC8|INC N]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |85 nn |
− | |[[ | + | |[[PM_Opc_INC8|INC [N+#nn]]] |
− | |16 | + | |16 |
− | | | + | |- |
− | + | |86 | |
− | + | |[[PM_Opc_INC8|INC [HL]]] | |
− | + | |12 | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | | | + | |87 |
− | |[[ | + | |[[PM_Opc_INC16|INC SP]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |90 |
− | |[[ | + | |[[PM_Opc_INC16|INC BA]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |91 |
− | |[[ | + | |[[PM_Opc_INC16|INC HL]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |92 |
− | |[[ | + | |[[PM_Opc_INC16|INC X1]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |93 |
− | |[[ | + | |[[PM_Opc_INC16|INC X2]] |
− | | | + | |8 |
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' Zero | ||
+ | |||
+ | == DEC = Decrease Register by 1 == | ||
+ | |||
+ | [[PM_Opc_DEC8|8 Bit Opcode overview]] | ||
+ | |||
+ | [[PM_Opc_DEC16|16 Bit Opcode overview]] | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | | | + | |88 |
− | |[[ | + | |[[PM_Opc_DEC8|DEC A]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |89 |
− | |[[ | + | |[[PM_Opc_DEC8|DEC B]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |8A |
− | |[[ | + | |[[PM_Opc_DEC8|DEC L]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |8B |
− | |[[ | + | |[[PM_Opc_DEC8|DEC H]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |8C |
− | |[[ | + | |[[PM_Opc_DEC8|DEC N]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |8D nn |
− | |[[ | + | |[[PM_Opc_DEC8|DEC [N+#nn]]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |8E |
− | |[[ | + | |[[PM_Opc_DEC8|DEC [HL]]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |8F |
− | |[[ | + | |[[PM_Opc_DEC16|DEC SP]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |98 |
− | |[[ | + | |[[PM_Opc_DEC16|DEC BA]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |99 |
− | |[[ | + | |[[PM_Opc_DEC16|DEC HL]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |9A |
− | |[[ | + | |[[PM_Opc_DEC16|DEC X1]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |9B |
− | |[[ | + | |[[PM_Opc_DEC16|DEC X2]] |
− | + | |8 | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | | | ||
|} | |} | ||
− | '''Flags Affected:''' Zero | + | '''Flags Affected:''' Zero |
− | == | + | == NEG = Negate == |
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 1,715: | Line 1,717: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |CE A4 |
− | |[[ | + | |[[PM_Opc_NEG|NEG A]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CE A5 |
− | |[[ | + | |[[PM_Opc_NEG|NEG B]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CE A6 |
− | |[[ | + | |[[PM_Opc_NEG|NEG [N+#nn]]] |
− | | | + | |20 |
|- | |- | ||
− | | | + | |CE A7 |
− | |[[ | + | |[[PM_Opc_NEG|NEG [HL]]] |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|16 | |16 | ||
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' All | ||
+ | |||
+ | == MUL = Multiply == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | | | + | |CE D8 |
− | |[[ | + | |[[PM_Opc_MUL|MUL L, A]] |
− | | | + | |48 |
− | |- | + | |} |
− | + | ||
− | + | '''Flags Affected:''' All | |
− | + | ||
+ | == DIV = Divide == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | | | + | |CE D9 |
− | |[[ | + | |[[PM_Opc_DIV|DIV HL, A]] |
− | | | + | |52 |
− | |- | + | |} |
− | + | ||
− | + | '''Flags Affected:''' All | |
− | + | ||
+ | '''Note:''' Can throw Division by Zero | ||
+ | |||
+ | = Logic = | ||
+ | |||
+ | == TST = Test Bits == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | | | + | |94 |
− | |[[ | + | |[[PM_Opc_TST|TST A, B]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |95 nn |
− | |[[ | + | |[[PM_Opc_TST|TST [HL], #nn]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |96 nn |
− | |[[ | + | |[[PM_Opc_TST|TST A, #nn]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |97 nn |
− | |[[ | + | |[[PM_Opc_TST|TST B, #nn]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |DC nn nn |
− | |[[ | + | |[[PM_Opc_TST|TST [N+#nn], #nn]] |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|16 | |16 | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|} | |} | ||
'''Flags Affected:''' Zero, Sign | '''Flags Affected:''' Zero, Sign | ||
− | == | + | == AND = Logical AND == |
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 1,809: | Line 1,805: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |20 |
− | |[[ | + | |[[PM_Opc_AND|AND A, A]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |21 |
− | |[[ | + | |[[PM_Opc_AND|AND A, B]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |22 nn |
− | |[[ | + | |[[PM_Opc_AND|AND A, #nn]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |23 |
− | |[[ | + | |[[PM_Opc_AND|AND A, [HL]]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |24 nn |
− | |[[ | + | |[[PM_Opc_AND|AND A, [N+#nn]]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |25 nn nn |
− | |[[ | + | |[[PM_Opc_AND|AND A, [#nnnn]]] |
|16 | |16 | ||
|- | |- | ||
− | | | + | |26 |
− | |[[ | + | |[[PM_Opc_AND|AND A, [X]]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |27 |
− | |[[ | + | |[[PM_Opc_AND|AND A, [Y]]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |9C nn |
− | |[[ | + | |[[PM_Opc_AND|AND F, #nn]] |
|12 | |12 | ||
|- | |- | ||
− | |CE | + | |CE B0 nn |
− | |[[ | + | |[[PM_Opc_AND|AND B, #nn]] |
|12 | |12 | ||
|- | |- | ||
− | |CE | + | |CE B1 nn |
− | |[[ | + | |[[PM_Opc_AND|AND L, #nn]] |
|12 | |12 | ||
|- | |- | ||
− | |CE | + | |CE B2 nn |
− | |[[ | + | |[[PM_Opc_AND|AND H, #nn]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |D8 nn nn |
− | |[[ | + | |[[PM_Opc_AND|AND [N+#nn], #nn]] |
|20 | |20 | ||
|- | |- | ||
− | |CE | + | |CE 20 ss |
− | |[[ | + | |[[PM_Opc_AND|AND A, [X+#ss]]] |
|16 | |16 | ||
|- | |- | ||
− | |CE | + | |CE 21 ss |
− | |[[ | + | |[[PM_Opc_AND|AND A, [Y+#ss]]] |
|16 | |16 | ||
|- | |- | ||
− | |CE | + | |CE 22 |
− | |[[ | + | |[[PM_Opc_AND|AND A, [X+L]]] |
|16 | |16 | ||
|- | |- | ||
− | |CE | + | |CE 23 |
− | |[[ | + | |[[PM_Opc_AND|AND A, [Y+L]]] |
|16 | |16 | ||
|- | |- | ||
− | |CE | + | |CE 24 |
− | |[[ | + | |[[PM_Opc_AND|AND [HL], A]] |
|16 | |16 | ||
|- | |- | ||
− | |CE | + | |CE 25 nn |
− | |[[ | + | |[[PM_Opc_AND|AND [HL], #nn]] |
|20 | |20 | ||
|- | |- | ||
− | |CE | + | |CE 26 |
− | |[[ | + | |[[PM_Opc_AND|AND [HL], [X]]] |
|20 | |20 | ||
|- | |- | ||
− | |CE | + | |CE 27 |
− | |[[ | + | |[[PM_Opc_AND|AND [HL], [Y]]] |
|20 | |20 | ||
|} | |} | ||
Line 1,896: | Line 1,892: | ||
'''Flags Affected:''' Zero, Sign | '''Flags Affected:''' Zero, Sign | ||
− | == | + | == OR = Logical Inclusive-OR == |
− | |||
− | |||
− | |||
− | |||
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 1,907: | Line 1,899: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |28 |
− | |[[ | + | |[[PM_Opc_OR|OR A, A]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |29 |
− | |[[ | + | |[[PM_Opc_OR|OR A, B]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |2A nn |
− | |[[ | + | |[[PM_Opc_OR|OR A, #nn]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |2B |
− | |[[ | + | |[[PM_Opc_OR|OR A, [HL]]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |2C nn |
− | |[[ | + | |[[PM_Opc_OR|OR A, [N+#nn]]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |2D nn nn |
− | |[[ | + | |[[PM_Opc_OR|OR A, [#nnnn]]] |
|16 | |16 | ||
|- | |- | ||
− | | | + | |2E |
− | |[[ | + | |[[PM_Opc_OR|OR A, [X]]] |
− | |||
− | |||
− | |||
− | |||
|8 | |8 | ||
|- | |- | ||
− | | | + | |2F |
− | |[[ | + | |[[PM_Opc_OR|OR A, [Y]]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |9D nn |
− | |[[ | + | |[[PM_Opc_OR|OR F, #nn]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CE B4 nn |
− | |[[ | + | |[[PM_Opc_OR|OR B, #nn]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CE B5 nn |
− | |[[ | + | |[[PM_Opc_OR|OR L, #nn]] |
− | | | + | |12 |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | | | + | |CE B6 nn |
− | |[[ | + | |[[PM_Opc_OR|OR H, #nn]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |D9 nn nn |
− | |[[ | + | |[[PM_Opc_OR|OR [N+#nn], #nn]] |
− | | | + | |20 |
|- | |- | ||
− | | | + | |CE 28 ss |
− | |[[ | + | |[[PM_Opc_OR|OR A, [X+#ss]]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |CE 29 ss |
− | |[[ | + | |[[PM_Opc_OR|OR A, [Y+#ss]]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |CE 2A |
− | |[[ | + | |[[PM_Opc_OR|OR A, [X+L]]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |CE 2B |
− | |[[ | + | |[[PM_Opc_OR|OR A, [Y+L]]] |
|16 | |16 | ||
|- | |- | ||
− | | | + | |CE 2C |
− | |[[ | + | |[[PM_Opc_OR|OR [HL], A]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |CE 2D nn |
− | |[[ | + | |[[PM_Opc_OR|OR [HL], #nn]] |
− | | | + | |20 |
|- | |- | ||
− | | | + | |CE 2E |
− | |[[ | + | |[[PM_Opc_OR|OR [HL], [X]]] |
− | | | + | |20 |
|- | |- | ||
− | | | + | |CE 2F |
− | |[[ | + | |[[PM_Opc_OR|OR [HL], [Y]]] |
− | + | |20 | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | | | ||
|} | |} | ||
− | '''Flags Affected:''' Zero | + | '''Flags Affected:''' Zero, Sign |
− | == | + | == XOR = Logical Exclusive-OR == |
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 2,027: | Line 1,993: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |38 |
− | |[[ | + | |[[PM_Opc_XOR|XOR A, A]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |39 |
− | |[[ | + | |[[PM_Opc_XOR|XOR A, B]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |3A nn |
− | |[[ | + | |[[PM_Opc_XOR|XOR A, #nn]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |3B |
− | |[[ | + | |[[PM_Opc_XOR|XOR A, [HL]]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |3C nn |
− | |[[ | + | |[[PM_Opc_XOR|XOR A, [N+#nn]]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |3D nn nn |
− | |[[ | + | |[[PM_Opc_XOR|XOR A, [#nnnn]]] |
− | | | + | |16 |
+ | |- | ||
+ | |3E | ||
+ | |[[PM_Opc_XOR|XOR A, [X]]] | ||
+ | |8 | ||
|- | |- | ||
− | | | + | |3F |
− | |[[ | + | |[[PM_Opc_XOR|XOR A, [Y]]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |9E nn |
− | |[[ | + | |[[PM_Opc_XOR|XOR F, #nn]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CE B8 nn |
− | |[[ | + | |[[PM_Opc_XOR|XOR B, #nn]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CE B9 nn |
− | |[[ | + | |[[PM_Opc_XOR|XOR L, #nn]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CE BA nn |
− | |[[ | + | |[[PM_Opc_XOR|XOR H, #nn]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |DA nn nn |
− | |[[ | + | |[[PM_Opc_XOR|XOR [N+#nn], #nn]] |
− | | | + | |20 |
|- | |- | ||
− | | | + | |CE 38 ss |
− | |[[ | + | |[[PM_Opc_XOR|XOR A, [X+#ss]]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |CE 39 ss |
− | |[[ | + | |[[PM_Opc_XOR|XOR A, [Y+#ss]]] |
− | | | + | |16 |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | | | + | |CE 3A |
− | |[[ | + | |[[PM_Opc_XOR|XOR A, [X+L]]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |CE 3B |
− | |[[ | + | |[[PM_Opc_XOR|XOR A, [Y+L]]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |CE 3C |
− | |[[ | + | |[[PM_Opc_XOR|XOR [HL], A]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |CE 3D nn |
− | |[[ | + | |[[PM_Opc_XOR|XOR [HL], #nn]] |
− | | | + | |20 |
|- | |- | ||
− | | | + | |CE 3E |
− | |[[ | + | |[[PM_Opc_XOR|XOR [HL], [X]]] |
− | | | + | |20 |
|- | |- | ||
− | | | + | |CE 3F |
− | |[[ | + | |[[PM_Opc_XOR|XOR [HL], [Y]]] |
− | | | + | |20 |
− | |- | + | |} |
− | + | ||
− | + | '''Flags Affected:''' Zero, Sign | |
− | + | ||
+ | == NOT = Logical NOT == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | | | + | |CE A0 |
− | |[[ | + | |[[PM_Opc_NOT|NOT A]] |
− | |||
− | |||
− | |||
− | |||
|12 | |12 | ||
|- | |- | ||
− | | | + | |CE A1 |
− | |[[ | + | |[[PM_Opc_NOT|NOT B]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CE A2 |
− | |[[ | + | |[[PM_Opc_NOT|NOT [N+#nn]]] |
− | | | + | |20 |
|- | |- | ||
− | | | + | |CE A3 |
− | |[[ | + | |[[PM_Opc_NOT|NOT [HL]]] |
− | + | |16 | |
− | |||
− | |||
− | |[ | ||
− | |||
− | |||
− | |||
− | |||
− | | | ||
|} | |} | ||
− | '''Flags Affected:''' | + | '''Flags Affected:''' Zero, Sign |
− | = | + | = Shift & Rotate = |
− | + | == SHL = Shift Left == | |
− | |||
− | |||
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 2,163: | Line 2,115: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |CE 84 |
− | |[[ | + | |[[PM_Opc_SHL|SHL A]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CE 85 |
− | |[[ | + | |[[PM_Opc_SHL|SHL B]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CE 86 |
− | |[[ | + | |[[PM_Opc_SHL|SHL [N+#nn]]] |
− | | | + | |20 |
|- | |- | ||
− | | | + | |CE 87 |
− | |[[ | + | |[[PM_Opc_SHL|SHL [HL]]] |
− | + | |16 | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | | | ||
|} | |} | ||
− | '''Flags Affected:''' | + | '''Flags Affected:''' Zero, Carry, Sign |
− | == | + | == SAL = Shift Alternative Left == |
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 2,197: | Line 2,141: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |CE 80 |
− | |[[ | + | |[[PM_Opc_SAL|SAL A]] |
− | | | + | |12 |
+ | |- | ||
+ | |CE 81 | ||
+ | |[[PM_Opc_SAL|SAL B]] | ||
+ | |12 | ||
+ | |- | ||
+ | |CE 82 | ||
+ | |[[PM_Opc_SAL|SAL [N+#nn]]] | ||
+ | |20 | ||
|- | |- | ||
− | | | + | |CE 83 |
− | |[[ | + | |[[PM_Opc_SAL|SAL [HL]]] |
− | | | + | |16 |
|} | |} | ||
− | '''Flags Affected:''' | + | '''Flags Affected:''' All |
− | == | + | == SHR = Shift Right == |
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 2,215: | Line 2,167: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |CE 8C |
− | |[[ | + | |[[PM_Opc_SHR|SHR A]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CE 8D |
− | |[[ | + | |[[PM_Opc_SHR|SHR B]] |
|12 | |12 | ||
+ | |- | ||
+ | |CE 8E | ||
+ | |[[PM_Opc_SHR|SHR [N+#nn]]] | ||
+ | |20 | ||
+ | |- | ||
+ | |CE 8F | ||
+ | |[[PM_Opc_SHR|SHR [HL]]] | ||
+ | |16 | ||
|} | |} | ||
− | '''Flags Affected:''' | + | '''Flags Affected:''' Zero, Carry, Sign |
− | == | + | == SAR = Shift Alternative Right == |
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 2,233: | Line 2,193: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |CE 88 |
− | |[[ | + | |[[PM_Opc_SAR|SAR A]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CE 89 |
− | |[[ | + | |[[PM_Opc_SAR|SAR B]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CE 8A |
− | |[[ | + | |[[PM_Opc_SAR|SAR [N+#nn]]] |
− | |20 | + | |20 |
|- | |- | ||
− | | | + | |CE 8B |
− | |[[ | + | |[[PM_Opc_SAR|SAR [HL]]] |
− | | | + | |16 |
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' All | ||
+ | |||
+ | == ROL = Rotate Left == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | | | + | |CE 94 |
− | |[[ | + | |[[PM_Opc_ROL|ROL A]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CE 95 |
− | |[[ | + | |[[PM_Opc_ROL|ROL B]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CE 96 |
− | |[[ | + | |[[PM_Opc_ROL|ROL [N+#nn]]] |
− | | | + | |20 |
|- | |- | ||
− | | | + | |CE 97 |
− | |[[ | + | |[[PM_Opc_ROL|ROL [HL]]] |
− | | | + | |16 |
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' Zero, Carry, Sign | ||
+ | |||
+ | == ROLC = Rotate Left though Carry == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | | | + | |CE 90 |
− | |[[ | + | |[[PM_Opc_ROLC|ROLC A]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CE 91 |
− | |[[ | + | |[[PM_Opc_ROLC|ROLC B]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CE 92 |
− | |[[ | + | |[[PM_Opc_ROLC|ROLC [N+#nn]]] |
|20 | |20 | ||
|- | |- | ||
− | | | + | |CE 93 |
− | |[[ | + | |[[PM_Opc_ROLC|ROLC [HL]]] |
− | | | + | |16 |
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' Zero, Carry, Sign | ||
+ | |||
+ | == ROR = Rotate Right == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | |CE | + | |CE 9C |
− | |[[ | + | |[[PM_Opc_ROR|ROR A]] |
− | | | + | |12 |
|- | |- | ||
− | |CE | + | |CE 9D |
− | |[[ | + | |[[PM_Opc_ROR|ROR B]] |
− | | | + | |12 |
|- | |- | ||
− | |CE | + | |CE 9E |
− | |[[ | + | |[[PM_Opc_ROR|ROR [N+#nn]]] |
− | | | + | |20 |
|- | |- | ||
− | |CE | + | |CE 9F |
− | |[[ | + | |[[PM_Opc_ROR|ROR [HL]]] |
− | | | + | |16 |
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' Zero, Carry, Sign | ||
+ | |||
+ | == RORC = Rotate Right though Carry == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | |CE | + | |CE 98 |
− | |[[ | + | |[[PM_Opc_RORC|RORC A]] |
− | | | + | |12 |
|- | |- | ||
− | |CE | + | |CE 99 |
− | |[[ | + | |[[PM_Opc_RORC|RORC B]] |
− | | | + | |12 |
|- | |- | ||
− | |CE | + | |CE 9A |
− | |[[ | + | |[[PM_Opc_RORC|RORC [N+#nn]]] |
− | | | + | |20 |
|- | |- | ||
− | |CE | + | |CE 9B |
− | |[[ | + | |[[PM_Opc_RORC|RORC [HL]]] |
− | | | + | |16 |
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' Zero, Carry, Sign | ||
+ | |||
+ | = Swap & Expand = | ||
+ | |||
+ | == XCHG = Exchange Registers == | ||
+ | |||
+ | [[PM_Opc_XCHG8|8 Bit Opcode overview]] | ||
+ | |||
+ | [[PM_Opc_XCHG16|16 Bit Opcode overview]] | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | | | + | |C8 |
− | |[[ | + | |[[PM_Opc_XCHG16|XCHG BA, HL]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |C9 |
− | |[[ | + | |[[PM_Opc_XCHG16|XCHG BA, X]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CA |
− | |[[ | + | |[[PM_Opc_XCHG16|XCHG BA, Y]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CB |
− | |[[ | + | |[[PM_Opc_XCHG16|XCHG BA, SP]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |CC |
− | |[[ | + | |[[PM_Opc_XCHG8|XCHG A, B]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |CD |
− | |[[ | + | |[[PM_Opc_XCHG8|XCHG A, [HL]]] |
− | + | |12 | |
− | |||
− | |||
− | |[ | ||
− | |||
− | |||
− | |||
− | |||
− | | | ||
|} | |} | ||
'''Flags Affected:''' None | '''Flags Affected:''' None | ||
− | == | + | == PACK = Pack and Unpack Nibbles == |
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 2,355: | Line 2,363: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |DE |
− | |[[ | + | |[[PM_Opc_PACK|PACK]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |DF |
− | |[[ | + | |[[PM_Opc_UNPACK|UNPACK]] |
|8 | |8 | ||
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' None | ||
+ | |||
+ | == SWAP = Swap Low and High Nibbles == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | | | + | |F6 |
− | |[[ | + | |[[PM_Opc_SWAP|SWAP A]] |
|8 | |8 | ||
|- | |- | ||
− | | | + | |F7 |
− | |[[ | + | |[[PM_Opc_SWAP|SWAP [HL]]] |
− | |||
− | |||
− | |||
− | |[ | ||
− | |||
− | |||
− | |||
− | |||
|12 | |12 | ||
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' None | ||
+ | |||
+ | == EX = Expand Register == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | | | + | |CE A8 |
− | |[[ | + | |[[PM_Opc_EX|EX BA, A]] |
|12 | |12 | ||
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' None | ||
+ | |||
+ | = Stack = | ||
+ | |||
+ | == PUSH = Push Register into Stack == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
|- | |- | ||
− | | | + | |A0 |
− | |[[ | + | |[[PM_Opc_PUSH1|PUSH BA]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |A1 |
− | |[[ | + | |[[PM_Opc_PUSH1|PUSH HL]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |A2 |
− | |[[ | + | |[[PM_Opc_PUSH1|PUSH X]] |
− | | | + | |16 |
|- | |- | ||
− | | | + | |A3 |
− | |[[ | + | |[[PM_Opc_PUSH1|PUSH Y]] |
− | |||
− | |||
− | |||
− | |||
|16 | |16 | ||
|- | |- | ||
− | | | + | |A4 |
− | |[[ | + | |[[PM_Opc_PUSH2|PUSH N]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |A5 |
− | |[[ | + | |[[PM_Opc_PUSH2|PUSH I]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |A6 |
− | |[[ | + | |[[PM_Opc_PUSHX|PUSHX]] |
+ | |16 | ||
+ | |- | ||
+ | |A7 | ||
+ | |[[PM_Opc_PUSH2|PUSH F]] | ||
|12 | |12 | ||
|- | |- | ||
− | | | + | |CF B0 |
− | |[[ | + | |[[PM_Opc_PUSH2|PUSH A]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CF B1 |
− | |[[ | + | |[[PM_Opc_PUSH2|PUSH B]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CF B2 |
− | |[[ | + | |[[PM_Opc_PUSH2|PUSH L]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CF B3 |
− | |[[ | + | |[[PM_Opc_PUSH2|PUSH H]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CF B8 |
− | |[[ | + | |[[PM_Opc_PUSHA|PUSHA]] |
+ | |48 | ||
+ | |- | ||
+ | |CF B9 | ||
+ | |[[PM_Opc_PUSHAX|PUSHAX]] | ||
+ | |60 | ||
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' None | ||
+ | |||
+ | == POP = Pop Register from Stack == | ||
+ | |||
+ | {| border="1" style="text-align:left" | ||
+ | !Hex | ||
+ | !Mnemonic | ||
+ | !Cycles | ||
+ | |- | ||
+ | |A8 | ||
+ | |[[PM_Opc_POP1|POP BA]] | ||
|12 | |12 | ||
|- | |- | ||
− | | | + | |A9 |
− | |[[ | + | |[[PM_Opc_POP1|POP HL]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |AA |
− | |[[ | + | |[[PM_Opc_POP1|POP X]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |AB |
− | |[[ | + | |[[PM_Opc_POP1|POP Y]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |AC |
− | |[[ | + | |[[PM_Opc_POP2|POP N]] |
+ | |8 | ||
+ | |- | ||
+ | |AD | ||
+ | |[[PM_Opc_POP2|POP I]] | ||
+ | |8 | ||
+ | |- | ||
+ | |AE | ||
+ | |[[PM_Opc_POPX|POPX]] | ||
|12 | |12 | ||
|- | |- | ||
− | | | + | |AF |
− | |[[ | + | |[[PM_Opc_POP2|POP F]] |
+ | |8 | ||
+ | |- | ||
+ | |CF B4 | ||
+ | |[[PM_Opc_POP2|POP A]] | ||
|12 | |12 | ||
|- | |- | ||
− | | | + | |CF B5 |
− | |[[ | + | |[[PM_Opc_POP2|POP B]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CF B6 |
− | |[[ | + | |[[PM_Opc_POP2|POP L]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CF B7 |
− | |[[ | + | |[[PM_Opc_POP2|POP H]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |CF BC |
− | |[[ | + | |[[PM_Opc_POPA|POPA]] |
− | | | + | |32 |
+ | |- | ||
+ | |CF BD | ||
+ | |[[PM_Opc_POPAX|POPAX]] | ||
+ | |40 | ||
|} | |} | ||
'''Flags Affected:''' None | '''Flags Affected:''' None | ||
− | == | + | = Branch = |
+ | |||
+ | == CALL = Call routine == | ||
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 2,481: | Line 2,549: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |E0 ss |
− | |[[ | + | |[[PM_Opc_CALLC|CALLC short #ss]] |
− | |8 | + | |20 / 8 (Not met) |
|- | |- | ||
− | | | + | |E1 ss |
− | |[[ | + | |[[PM_Opc_CALLC|CALLNC short #ss]] |
− | |8 | + | |20 / 8 (Not met) |
|- | |- | ||
− | | | + | |E2 ss |
− | |[[ | + | |[[PM_Opc_CALLC|CALLZ short #ss]] |
− | |8 | + | |20 / 8 (Not met) |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | | | + | |E3 ss |
− | |[[ | + | |[[PM_Opc_CALLC|CALLNZ short #ss]] |
− | | | + | |20 / 8 (Not met) |
|- | |- | ||
− | | | + | |E8 ss ss |
− | |[[ | + | |[[PM_Opc_CALLC|CALLC long #ssss]] |
− | |12 | + | |24 / 12 (Not met) |
|- | |- | ||
− | | | + | |E9 ss ss |
− | |[[ | + | |[[PM_Opc_CALLC|CALLNC long #ssss]] |
− | | | + | |24 / 12 (Not met) |
|- | |- | ||
− | | | + | |EA ss ss |
− | |[[ | + | |[[PM_Opc_CALLC|CALLZ long #ssss]] |
− | | | + | |24 / 12 (Not met) |
− | | | + | |- |
− | + | |EB ss ss | |
− | + | |[[PM_Opc_CALLC|CALLNZ long #ssss]] | |
− | + | |24 / 12 (Not met) | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | | | + | |F0 ss |
− | |[[ | + | |[[PM_Opc_CALL|CALL short #ss]] |
− | | | + | |20 |
|- | |- | ||
− | | | + | |F2 ss ss |
− | |[[ | + | |[[PM_Opc_CALL|CALL long #ssss]] |
− | | | + | |24 |
|- | |- | ||
− | | | + | |FB ss ss |
− | |[[ | + | |[[PM_Opc_CALL|CALL [#nnnn]]] |
|20 | |20 | ||
|- | |- | ||
− | | | + | |FC ss |
− | |[[ | + | |[[PM_Opc_CINT|CINT #nn]] |
− | | | + | |20 |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | |CE | + | |CE F0 ss |
− | |[[ | + | |[[PM_Opc_CALLE|CALLL short #ss]] |
− | |12 | + | |24 / 12 (Not met) |
|- | |- | ||
− | |CE | + | |CE F1 ss |
− | |[[ | + | |[[PM_Opc_CALLE|CALLLE short #ss]] |
− | |12 | + | |24 / 12 (Not met) |
|- | |- | ||
− | |CE | + | |CE F2 ss |
− | |[[ | + | |[[PM_Opc_CALLE|CALLG short #ss]] |
− | | | + | |24 / 12 (Not met) |
|- | |- | ||
− | |CE | + | |CE F3 ss |
− | |[[ | + | |[[PM_Opc_CALLE|CALLGE short #ss]] |
− | | | + | |24 / 12 (Not met) |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | |CE | + | |CE F4 ss |
− | |[[ | + | |[[PM_Opc_CALLE|CALLO short #ss]] |
− | |12 | + | |24 / 12 (Not met) |
|- | |- | ||
− | |CE | + | |CE F5 ss |
− | |[[ | + | |[[PM_Opc_CALLE|CALLNO short #ss]] |
− | |12 | + | |24 / 12 (Not met) |
|- | |- | ||
− | |CE | + | |CE F6 ss |
− | |[[ | + | |[[PM_Opc_CALLE|CALLP short #ss]] |
− | | | + | |24 / 12 (Not met) |
|- | |- | ||
− | |CE | + | |CE F7 ss |
− | |[[ | + | |[[PM_Opc_CALLE|CALLNP short #ss]] |
− | | | + | |24 / 12 (Not met) |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | |CE | + | |CE F8 ss |
− | |[[ | + | |[[PM_Opc_CALLX|CALLNX0 short #ss]] |
− | |12 | + | |24 / 12 (Not met) |
|- | |- | ||
− | |CE | + | |CE F9 ss |
− | |[[ | + | |[[PM_Opc_CALLX|CALLNX1 short #ss]] |
− | |12 | + | |24 / 12 (Not met) |
|- | |- | ||
− | |CE | + | |CE FA ss |
− | |[[ | + | |[[PM_Opc_CALLX|CALLNX2 short #ss]] |
− | | | + | |24 / 12 (Not met) |
|- | |- | ||
− | |CE | + | |CE FB ss |
− | |[[ | + | |[[PM_Opc_CALLX|CALLNX3 short #ss]] |
− | | | + | |24 / 12 (Not met) |
+ | |- | ||
+ | |CE FC ss | ||
+ | |[[PM_Opc_CALLX|CALLX0 short #ss]] | ||
+ | |24 / 12 (Not met) | ||
+ | |- | ||
+ | |CE FD ss | ||
+ | |[[PM_Opc_CALLX|CALLX1 short #ss]] | ||
+ | |24 / 12 (Not met) | ||
+ | |- | ||
+ | |CE FE ss | ||
+ | |[[PM_Opc_CALLX|CALLX2 short #ss]] | ||
+ | |24 / 12 (Not met) | ||
+ | |- | ||
+ | |CE FF ss | ||
+ | |[[PM_Opc_CALLX|CALLX3 short #ss]] | ||
+ | |24 / 12 (Not met) | ||
|} | |} | ||
− | '''Flags Affected:''' | + | '''Flags Affected:''' None |
− | == | + | == JMP = Jump to routine == |
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 2,633: | Line 2,671: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |E4 ss |
− | |[[ | + | |[[PM_Opc_JMPC|JC short #ss]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |E5 ss |
− | |[[ | + | |[[PM_Opc_JMPC|JNC short #ss]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |E6 ss |
− | |[[ | + | |[[PM_Opc_JMPC|JZ short #ss]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |E7 ss |
− | |[[ | + | |[[PM_Opc_JMPC|JNZ short #ss]] |
− | | | + | |8 |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | | | + | |EC ss ss |
− | |[[ | + | |[[PM_Opc_JMPC|JC long #ssss]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |ED ss ss |
− | |[[ | + | |[[PM_Opc_JMPC|JNC long #ssss]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |EE ss ss |
− | |[[ | + | |[[PM_Opc_JMPC|JZ long #ssss]] |
− | | | + | |12 |
|- | |- | ||
− | | | + | |EF ss ss |
− | |[[ | + | |[[PM_Opc_JMPC|JNZ long #ssss]] |
− | | | + | |12 |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | | | + | |F1 ss |
− | |[[ | + | |[[PM_Opc_JMP|JMP short #ss]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |F3 ss ss |
− | |[[ | + | |[[PM_Opc_JMP|JMP long #ssss]] |
|12 | |12 | ||
|- | |- | ||
− | | | + | |F4 |
− | |[[ | + | |[[PM_Opc_JMPHL|JMP HL]] |
− | | | + | |8 |
|- | |- | ||
− | | | + | |F5 ss |
− | |[[ | + | |[[PM_Opc_JDBNZ|JDBNZ short #ss]] |
|16 | |16 | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | |CE | + | |FD ss |
− | |[[ | + | |[[PM_Opc_JINT|JINT #nn]] |
+ | |8 | ||
+ | |- | ||
+ | |CE E0 ss | ||
+ | |[[PM_Opc_JMPE|JL short #ss]] | ||
+ | |12 | ||
+ | |- | ||
+ | |CE E1 ss | ||
+ | |[[PM_Opc_JMPE|JLE short #ss]] | ||
|12 | |12 | ||
|- | |- | ||
− | |CE | + | |CE E2 ss |
− | |[[ | + | |[[PM_Opc_JMPE|JG short #ss]] |
|12 | |12 | ||
|- | |- | ||
− | |CE | + | |CE E3 ss |
− | |[[ | + | |[[PM_Opc_JMPE|JGE short #ss]] |
− | | | + | |12 |
|- | |- | ||
− | |CE | + | |CE E4 ss |
− | |[[ | + | |[[PM_Opc_JMPE|JO short #ss]] |
− | | | + | |12 |
− | | | + | |- |
− | + | |CE E5 ss | |
− | + | |[[PM_Opc_JMPE|JNO short #ss]] | |
− | + | |12 | |
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
|- | |- | ||
− | |CE | + | |CE E6 ss |
− | |[[ | + | |[[PM_Opc_JMPE|JP short #ss]] |
|12 | |12 | ||
|- | |- | ||
− | |CE | + | |CE E7 ss |
− | |[[ | + | |[[PM_Opc_JMPE|JNP short #ss]] |
|12 | |12 | ||
|- | |- | ||
− | |CE | + | |CE E8 ss |
− | |[[ | + | |[[PM_Opc_JMPX|JNX0 short #ss]] |
− | | | + | |12 |
|- | |- | ||
− | |CE | + | |CE E9 ss |
− | |[[ | + | |[[PM_Opc_JMPX|JNX1 short #ss]] |
− | | | + | |12 |
− | |} | + | |- |
+ | |CE EA ss | ||
+ | |[[PM_Opc_JMPX|JNX2 short #ss]] | ||
+ | |12 | ||
+ | |- | ||
+ | |CE EB ss | ||
+ | |[[PM_Opc_JMPX|JNX3 short #ss]] | ||
+ | |12 | ||
+ | |- | ||
+ | |CE EC ss | ||
+ | |[[PM_Opc_JMPX|JX0 short #ss]] | ||
+ | |12 | ||
+ | |- | ||
+ | |CE ED ss | ||
+ | |[[PM_Opc_JMPX|JX1 short #ss]] | ||
+ | |12 | ||
+ | |- | ||
+ | |CE EE ss | ||
+ | |[[PM_Opc_JMPX|JX2 short #ss]] | ||
+ | |12 | ||
+ | |- | ||
+ | |CE EF ss | ||
+ | |[[PM_Opc_JMPX|JX3 short #ss]] | ||
+ | |12 | ||
+ | |} | ||
− | '''Flags Affected:''' | + | '''Flags Affected:''' None |
− | == | + | == RET = Return from routine == |
{| border="1" style="text-align:left" | {| border="1" style="text-align:left" | ||
Line 2,763: | Line 2,797: | ||
!Cycles | !Cycles | ||
|- | |- | ||
− | | | + | |F8 |
− | |[[ | + | |[[PM_Opc_RET|RET]] |
− | | | + | |8 |
− | |} | + | |- |
+ | |F9 | ||
+ | |[[PM_Opc_RETI|RETI]] | ||
+ | |8 | ||
+ | |- | ||
+ | |FA | ||
+ | |[[PM_Opc_RETSKIP|RETSKIP]] | ||
+ | |8 | ||
+ | |} | ||
+ | |||
+ | '''Flags Affected:''' None | ||
− | + | = System = | |
== HALT = Halt CPU == | == HALT = Halt CPU == | ||
Line 2,797: | Line 2,841: | ||
'''Flags Affected:''' None | '''Flags Affected:''' None | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− |
Revision as of 15:23, 12 June 2008
Move
NOP = No Operation
Hex | Mnemonic | Cycles |
---|---|---|
FF | NOP | 8 |
Flags Affected: None
MOV = Move Register
Flags Affected: None
Arithmetic
ADD = Addition
Hex | Mnemonic | Cycles |
---|---|---|
00 | ADD A, A | 8 |
01 | ADD A, B | 8 |
02 nn | ADD A, #nn | 8 |
03 | ADD A, [HL] | 8 |
04 nn | ADD A, [N+#nn] | 12 |
05 nn nn | ADD A, [#nnnn] | 16 |
06 | ADD A, [X] | 8 |
07 | ADD A, [Y] | 8 |
C0 nn nn | ADD BA, #nnnn | 12 |
C1 nn nn | ADD HL, #nnnn | 12 |
C2 nn nn | ADD X, #nnnn | 12 |
C3 nn nn | ADD Y, #nnnn | 12 |
CF 68 nn nn | ADD SP, #nnnn | 16 |
CE 00 ss | ADD A, [X+#ss] | 16 |
CE 01 ss | ADD A, [Y+#ss] | 16 |
CE 02 | ADD A, [X+L] | 16 |
CE 03 | ADD A, [Y+L] | 16 |
CE 04 | ADD [HL], A | 16 |
CE 05 nn | ADD [HL], #nn | 20 |
CE 06 | ADD [HL], [X] | 20 |
CE 07 | ADD [HL], [Y] | 20 |
CF 00 | ADD BA, BA | 16 |
CF 01 | ADD BA, HL | 16 |
CF 02 | ADD BA, X | 16 |
CF 03 | ADD BA, Y | 16 |
CF 20 | ADD HL, BA | 16 |
CF 21 | ADD HL, HL | 16 |
CF 22 | ADD HL, X | 16 |
CF 23 | ADD HL, Y | 16 |
CF 40 | ADD X, BA | 16 |
CF 41 | ADD X, HL | 16 |
CF 42 | ADD Y, BA | 16 |
CF 43 | ADD Y, HL | 16 |
CF 44 | ADD SP, BA | 16 |
CF 45 | ADD SP, HL | 16 |
Flags Affected: All
SUB = Subtraction
Hex | Mnemonic | Cycles |
---|---|---|
10 | SUB A, A | 8 |
11 | SUB A, B | 8 |
12 nn | SUB A, #nn | 8 |
13 | SUB A, [HL] | 8 |
14 nn | SUB A, [N+#nn] | 12 |
15 nn nn | SUB A, [#nnnn] | 16 |
16 | SUB A, [X] | 8 |
17 | SUB A, [Y] | 8 |
D0 nn nn | SUB BA, #nnnn | 12 |
D1 nn nn | SUB HL, #nnnn | 12 |
D2 nn nn | SUB X, #nnnn | 12 |
D3 nn nn | SUB Y, #nnnn | 12 |
CF 6A nn nn | SUB SP, #nnnn | 16 |
CE 10 ss | SUB A, [X+#ss] | 16 |
CE 11 ss | SUB A, [Y+#ss] | 16 |
CE 12 | SUB A, [X+L] | 16 |
CE 13 | SUB A, [Y+L] | 16 |
CE 14 | SUB [HL], A | 16 |
CE 15 nn | SUB [HL], #nn | 20 |
CE 16 | SUB [HL], [X] | 20 |
CE 17 | SUB [HL], [Y] | 20 |
CF 08 | SUB BA, BA | 16 |
CF 09 | SUB BA, HL | 16 |
CF 0A | SUB BA, X | 16 |
CF 0B | SUB BA, Y | 16 |
CF 28 | SUB HL, BA | 16 |
CF 29 | SUB HL, HL | 16 |
CF 2A | SUB HL, X | 16 |
CF 2B | SUB HL, Y | 16 |
CF 48 | SUB X, BA | 16 |
CF 49 | SUB X, HL | 16 |
CF 4A | SUB Y, BA | 16 |
CF 4B | SUB Y, HL | 16 |
CF 4C | SUB SP, BA | 16 |
CF 4D | SUB SP, HL | 16 |
Flags Affected: All
ADC = Addition with Carry
Hex | Mnemonic | Cycles |
---|---|---|
08 | ADC A, A | 8 |
09 | ADC A, B | 8 |
0A nn | ADC A, #nn | 8 |
0B | ADC A, [HL] | 8 |
0C nn | ADC A, [N+#nn] | 12 |
0D nn nn | ADC A, [#nnnn] | 16 |
0E | ADC A, [X] | 8 |
0F | ADC A, [Y] | 8 |
CE 08 ss | ADC A, [X+#ss] | 16 |
CE 09 ss | ADC A, [Y+#ss] | 16 |
CE 0A | ADC A, [X+L] | 16 |
CE 0B | ADC A, [Y+L] | 16 |
CE 0C | ADC [HL], A | 16 |
CE 0D nn | ADC [HL], #nn | 20 |
CE 0E | ADC [HL], [X] | 20 |
CE 0F | ADC [HL], [Y] | 20 |
CF 04 | ADC BA, BA | 16 |
CF 05 | ADC BA, HL | 16 |
CF 06 | ADC BA, X | 16 |
CF 07 | ADC BA, Y | 16 |
CF 24 | ADC HL, BA | 16 |
CF 25 | ADC HL, HL | 16 |
CF 26 | ADC HL, X | 16 |
CF 27 | ADC HL, Y | 16 |
CF 60 nn nn | ADC BA, #nnnn | 16 |
CF 61 nn nn | ADC HL, #nnnn | 16 |
Flags Affected: All
SBC = Subtraction with Carry
Hex | Mnemonic | Cycles |
---|---|---|
18 | SBC A, A | 8 |
19 | SBC A, B | 8 |
1A nn | SBC A, #nn | 8 |
1B | SBC A, [HL] | 8 |
1C nn | SBC A, [N+#nn] | 12 |
1D nn nn | SBC A, [#nnnn] | 16 |
1E | SBC A, [X] | 8 |
1F | SBC A, [Y] | 8 |
CE 18 ss | SBC A, [X+#ss] | 16 |
CE 19 ss | SBC A, [Y+#ss] | 16 |
CE 1A | SBC A, [X+L] | 16 |
CE 1B | SBC A, [Y+L] | 16 |
CE 1C | SBC [HL], A | 16 |
CE 1D nn | SBC [HL], #nn | 20 |
CE 1E | SBC [HL], [X] | 20 |
CE 1F | SBC [HL], [Y] | 20 |
CF 0C | SBC BA, BA | 16 |
CF 0D | SBC BA, HL | 16 |
CF 0E | SBC BA, X | 16 |
CF 0F | SBC BA, Y | 16 |
CF 2C | SBC HL, BA | 16 |
CF 2D | SBC HL, HL | 16 |
CF 2E | SBC HL, X | 16 |
CF 2F | SBC HL, Y | 16 |
CF 62 nn nn | SBC BA, #nnnn | 16 |
CF 63 nn nn | SBC HL, #nnnn | 16 |
Flags Affected: All
CMP = Compare
Hex | Mnemonic | Cycles |
---|---|---|
30 | CMP A, A | 8 |
31 | CMP A, B | 8 |
32 nn | CMP A, #nn | 8 |
33 | CMP A, [HL] | 8 |
34 nn | CMP A, [N+#nn] | 12 |
35 nn nn | CMP A, [#nnnn] | 16 |
36 | CMP A, [X] | 8 |
37 | CMP A, [Y] | 8 |
D4 nn nn | CMP BA, #nnnn | 12 |
D5 nn nn | CMP HL, #nnnn | 12 |
D6 nn nn | CMP X, #nnnn | 12 |
D7 nn nn | CMP Y, #nnnn | 12 |
CF 6C nn nn | CMP SP, #nnnn | 16 |
DB nn nn | CMP [N+#nn], #nn | 16 |
CE 30 ss | CMP A, [X+#ss] | 16 |
CE 31 ss | CMP A, [Y+#ss] | 16 |
CE 32 | CMP A, [X+L] | 16 |
CE 33 | CMP A, [Y+L] | 16 |
CE 34 | CMP [HL], A | 16 |
CE 35 nn | CMP [HL], #nn | 20 |
CE 36 | CMP [HL], [X] | 20 |
CE 37 | CMP [HL], [Y] | 20 |
CE BC nn | CMP B, #nn | 12 |
CE BD nn | CMP L, #nn | 12 |
CE BE nn | CMP H, #nn | 12 |
CF 18 | CMP BA, BA | 16 |
CF 19 | CMP BA, HL | 16 |
CF 1A | CMP BA, X | 16 |
CF 1B | CMP BA, Y | 16 |
CF 38 | CMP HL, BA | 16 |
CF 39 | CMP HL, HL | 16 |
CF 3A | CMP HL, X | 16 |
CF 3B | CMP HL, Y | 16 |
CF 5C | CMP SP, BA | 16 |
CF 5D | CMP SP, HL | 16 |
Flags Affected: All
INC = Increase Register by 1
Hex | Mnemonic | Cycles |
---|---|---|
80 | INC A | 8 |
81 | INC B | 8 |
82 | INC L | 8 |
83 | INC H | 8 |
84 | INC N | 8 |
85 nn | INC [N+#nn] | 16 |
86 | INC [HL] | 12 |
87 | INC SP | 8 |
90 | INC BA | 8 |
91 | INC HL | 8 |
92 | INC X1 | 8 |
93 | INC X2 | 8 |
Flags Affected: Zero
DEC = Decrease Register by 1
Hex | Mnemonic | Cycles |
---|---|---|
88 | DEC A | 8 |
89 | DEC B | 8 |
8A | DEC L | 8 |
8B | DEC H | 8 |
8C | DEC N | 8 |
8D nn | DEC [N+#nn] | 16 |
8E | DEC [HL] | 12 |
8F | DEC SP | 8 |
98 | DEC BA | 8 |
99 | DEC HL | 8 |
9A | DEC X1 | 8 |
9B | DEC X2 | 8 |
Flags Affected: Zero
NEG = Negate
Hex | Mnemonic | Cycles |
---|---|---|
CE A4 | NEG A | 12 |
CE A5 | NEG B | 12 |
CE A6 | NEG [N+#nn] | 20 |
CE A7 | NEG [HL] | 16 |
Flags Affected: All
MUL = Multiply
Hex | Mnemonic | Cycles |
---|---|---|
CE D8 | MUL L, A | 48 |
Flags Affected: All
DIV = Divide
Hex | Mnemonic | Cycles |
---|---|---|
CE D9 | DIV HL, A | 52 |
Flags Affected: All
Note: Can throw Division by Zero
Logic
TST = Test Bits
Hex | Mnemonic | Cycles |
---|---|---|
94 | TST A, B | 8 |
95 nn | TST [HL], #nn | 12 |
96 nn | TST A, #nn | 8 |
97 nn | TST B, #nn | 8 |
DC nn nn | TST [N+#nn], #nn | 16 |
Flags Affected: Zero, Sign
AND = Logical AND
Hex | Mnemonic | Cycles |
---|---|---|
20 | AND A, A | 8 |
21 | AND A, B | 8 |
22 nn | AND A, #nn | 8 |
23 | AND A, [HL] | 8 |
24 nn | AND A, [N+#nn] | 12 |
25 nn nn | AND A, [#nnnn] | 16 |
26 | AND A, [X] | 8 |
27 | AND A, [Y] | 8 |
9C nn | AND F, #nn | 12 |
CE B0 nn | AND B, #nn | 12 |
CE B1 nn | AND L, #nn | 12 |
CE B2 nn | AND H, #nn | 12 |
D8 nn nn | AND [N+#nn], #nn | 20 |
CE 20 ss | AND A, [X+#ss] | 16 |
CE 21 ss | AND A, [Y+#ss] | 16 |
CE 22 | AND A, [X+L] | 16 |
CE 23 | AND A, [Y+L] | 16 |
CE 24 | AND [HL], A | 16 |
CE 25 nn | AND [HL], #nn | 20 |
CE 26 | AND [HL], [X] | 20 |
CE 27 | AND [HL], [Y] | 20 |
Flags Affected: Zero, Sign
OR = Logical Inclusive-OR
Hex | Mnemonic | Cycles |
---|---|---|
28 | OR A, A | 8 |
29 | OR A, B | 8 |
2A nn | OR A, #nn | 8 |
2B | OR A, [HL] | 8 |
2C nn | OR A, [N+#nn] | 12 |
2D nn nn | OR A, [#nnnn] | 16 |
2E | OR A, [X] | 8 |
2F | OR A, [Y] | 8 |
9D nn | OR F, #nn | 12 |
CE B4 nn | OR B, #nn | 12 |
CE B5 nn | OR L, #nn | 12 |
CE B6 nn | OR H, #nn | 12 |
D9 nn nn | OR [N+#nn], #nn | 20 |
CE 28 ss | OR A, [X+#ss] | 16 |
CE 29 ss | OR A, [Y+#ss] | 16 |
CE 2A | OR A, [X+L] | 16 |
CE 2B | OR A, [Y+L] | 16 |
CE 2C | OR [HL], A | 16 |
CE 2D nn | OR [HL], #nn | 20 |
CE 2E | OR [HL], [X] | 20 |
CE 2F | OR [HL], [Y] | 20 |
Flags Affected: Zero, Sign
XOR = Logical Exclusive-OR
Hex | Mnemonic | Cycles |
---|---|---|
38 | XOR A, A | 8 |
39 | XOR A, B | 8 |
3A nn | XOR A, #nn | 8 |
3B | XOR A, [HL] | 8 |
3C nn | XOR A, [N+#nn] | 12 |
3D nn nn | XOR A, [#nnnn] | 16 |
3E | XOR A, [X] | 8 |
3F | XOR A, [Y] | 8 |
9E nn | XOR F, #nn | 12 |
CE B8 nn | XOR B, #nn | 12 |
CE B9 nn | XOR L, #nn | 12 |
CE BA nn | XOR H, #nn | 12 |
DA nn nn | XOR [N+#nn], #nn | 20 |
CE 38 ss | XOR A, [X+#ss] | 16 |
CE 39 ss | XOR A, [Y+#ss] | 16 |
CE 3A | XOR A, [X+L] | 16 |
CE 3B | XOR A, [Y+L] | 16 |
CE 3C | XOR [HL], A | 16 |
CE 3D nn | XOR [HL], #nn | 20 |
CE 3E | XOR [HL], [X] | 20 |
CE 3F | XOR [HL], [Y] | 20 |
Flags Affected: Zero, Sign
NOT = Logical NOT
Hex | Mnemonic | Cycles |
---|---|---|
CE A0 | NOT A | 12 |
CE A1 | NOT B | 12 |
CE A2 | NOT [N+#nn] | 20 |
CE A3 | NOT [HL] | 16 |
Flags Affected: Zero, Sign
Shift & Rotate
SHL = Shift Left
Hex | Mnemonic | Cycles |
---|---|---|
CE 84 | SHL A | 12 |
CE 85 | SHL B | 12 |
CE 86 | SHL [N+#nn] | 20 |
CE 87 | SHL [HL] | 16 |
Flags Affected: Zero, Carry, Sign
SAL = Shift Alternative Left
Hex | Mnemonic | Cycles |
---|---|---|
CE 80 | SAL A | 12 |
CE 81 | SAL B | 12 |
CE 82 | SAL [N+#nn] | 20 |
CE 83 | SAL [HL] | 16 |
Flags Affected: All
SHR = Shift Right
Hex | Mnemonic | Cycles |
---|---|---|
CE 8C | SHR A | 12 |
CE 8D | SHR B | 12 |
CE 8E | SHR [N+#nn] | 20 |
CE 8F | SHR [HL] | 16 |
Flags Affected: Zero, Carry, Sign
SAR = Shift Alternative Right
Hex | Mnemonic | Cycles |
---|---|---|
CE 88 | SAR A | 12 |
CE 89 | SAR B | 12 |
CE 8A | SAR [N+#nn] | 20 |
CE 8B | SAR [HL] | 16 |
Flags Affected: All
ROL = Rotate Left
Hex | Mnemonic | Cycles |
---|---|---|
CE 94 | ROL A | 12 |
CE 95 | ROL B | 12 |
CE 96 | ROL [N+#nn] | 20 |
CE 97 | ROL [HL] | 16 |
Flags Affected: Zero, Carry, Sign
ROLC = Rotate Left though Carry
Hex | Mnemonic | Cycles |
---|---|---|
CE 90 | ROLC A | 12 |
CE 91 | ROLC B | 12 |
CE 92 | ROLC [N+#nn] | 20 |
CE 93 | ROLC [HL] | 16 |
Flags Affected: Zero, Carry, Sign
ROR = Rotate Right
Hex | Mnemonic | Cycles |
---|---|---|
CE 9C | ROR A | 12 |
CE 9D | ROR B | 12 |
CE 9E | ROR [N+#nn] | 20 |
CE 9F | ROR [HL] | 16 |
Flags Affected: Zero, Carry, Sign
RORC = Rotate Right though Carry
Hex | Mnemonic | Cycles |
---|---|---|
CE 98 | RORC A | 12 |
CE 99 | RORC B | 12 |
CE 9A | RORC [N+#nn] | 20 |
CE 9B | RORC [HL] | 16 |
Flags Affected: Zero, Carry, Sign
Swap & Expand
XCHG = Exchange Registers
Hex | Mnemonic | Cycles |
---|---|---|
C8 | XCHG BA, HL | 12 |
C9 | XCHG BA, X | 12 |
CA | XCHG BA, Y | 12 |
CB | XCHG BA, SP | 12 |
CC | XCHG A, B | 8 |
CD | XCHG A, [HL] | 12 |
Flags Affected: None
PACK = Pack and Unpack Nibbles
Hex | Mnemonic | Cycles |
---|---|---|
DE | PACK | 8 |
DF | UNPACK | 8 |
Flags Affected: None
SWAP = Swap Low and High Nibbles
Hex | Mnemonic | Cycles |
---|---|---|
F6 | SWAP A | 8 |
F7 | SWAP [HL] | 12 |
Flags Affected: None
EX = Expand Register
Hex | Mnemonic | Cycles |
---|---|---|
CE A8 | EX BA, A | 12 |
Flags Affected: None
Stack
PUSH = Push Register into Stack
Hex | Mnemonic | Cycles |
---|---|---|
A0 | PUSH BA | 16 |
A1 | PUSH HL | 16 |
A2 | PUSH X | 16 |
A3 | PUSH Y | 16 |
A4 | PUSH N | 12 |
A5 | PUSH I | 12 |
A6 | PUSHX | 16 |
A7 | PUSH F | 12 |
CF B0 | PUSH A | 12 |
CF B1 | PUSH B | 12 |
CF B2 | PUSH L | 12 |
CF B3 | PUSH H | 12 |
CF B8 | PUSHA | 48 |
CF B9 | PUSHAX | 60 |
Flags Affected: None
POP = Pop Register from Stack
Hex | Mnemonic | Cycles |
---|---|---|
A8 | POP BA | 12 |
A9 | POP HL | 12 |
AA | POP X | 12 |
AB | POP Y | 12 |
AC | POP N | 8 |
AD | POP I | 8 |
AE | POPX | 12 |
AF | POP F | 8 |
CF B4 | POP A | 12 |
CF B5 | POP B | 12 |
CF B6 | POP L | 12 |
CF B7 | POP H | 12 |
CF BC | POPA | 32 |
CF BD | POPAX | 40 |
Flags Affected: None
Branch
CALL = Call routine
Hex | Mnemonic | Cycles |
---|---|---|
E0 ss | CALLC short #ss | 20 / 8 (Not met) |
E1 ss | CALLNC short #ss | 20 / 8 (Not met) |
E2 ss | CALLZ short #ss | 20 / 8 (Not met) |
E3 ss | CALLNZ short #ss | 20 / 8 (Not met) |
E8 ss ss | CALLC long #ssss | 24 / 12 (Not met) |
E9 ss ss | CALLNC long #ssss | 24 / 12 (Not met) |
EA ss ss | CALLZ long #ssss | 24 / 12 (Not met) |
EB ss ss | CALLNZ long #ssss | 24 / 12 (Not met) |
F0 ss | CALL short #ss | 20 |
F2 ss ss | CALL long #ssss | 24 |
FB ss ss | CALL [#nnnn] | 20 |
FC ss | CINT #nn | 20 |
CE F0 ss | CALLL short #ss | 24 / 12 (Not met) |
CE F1 ss | CALLLE short #ss | 24 / 12 (Not met) |
CE F2 ss | CALLG short #ss | 24 / 12 (Not met) |
CE F3 ss | CALLGE short #ss | 24 / 12 (Not met) |
CE F4 ss | CALLO short #ss | 24 / 12 (Not met) |
CE F5 ss | CALLNO short #ss | 24 / 12 (Not met) |
CE F6 ss | CALLP short #ss | 24 / 12 (Not met) |
CE F7 ss | CALLNP short #ss | 24 / 12 (Not met) |
CE F8 ss | CALLNX0 short #ss | 24 / 12 (Not met) |
CE F9 ss | CALLNX1 short #ss | 24 / 12 (Not met) |
CE FA ss | CALLNX2 short #ss | 24 / 12 (Not met) |
CE FB ss | CALLNX3 short #ss | 24 / 12 (Not met) |
CE FC ss | CALLX0 short #ss | 24 / 12 (Not met) |
CE FD ss | CALLX1 short #ss | 24 / 12 (Not met) |
CE FE ss | CALLX2 short #ss | 24 / 12 (Not met) |
CE FF ss | CALLX3 short #ss | 24 / 12 (Not met) |
Flags Affected: None
JMP = Jump to routine
Hex | Mnemonic | Cycles |
---|---|---|
E4 ss | JC short #ss | 8 |
E5 ss | JNC short #ss | 8 |
E6 ss | JZ short #ss | 8 |
E7 ss | JNZ short #ss | 8 |
EC ss ss | JC long #ssss | 12 |
ED ss ss | JNC long #ssss | 12 |
EE ss ss | JZ long #ssss | 12 |
EF ss ss | JNZ long #ssss | 12 |
F1 ss | JMP short #ss | 8 |
F3 ss ss | JMP long #ssss | 12 |
F4 | JMP HL | 8 |
F5 ss | JDBNZ short #ss | 16 |
FD ss | JINT #nn | 8 |
CE E0 ss | JL short #ss | 12 |
CE E1 ss | JLE short #ss | 12 |
CE E2 ss | JG short #ss | 12 |
CE E3 ss | JGE short #ss | 12 |
CE E4 ss | JO short #ss | 12 |
CE E5 ss | JNO short #ss | 12 |
CE E6 ss | JP short #ss | 12 |
CE E7 ss | JNP short #ss | 12 |
CE E8 ss | JNX0 short #ss | 12 |
CE E9 ss | JNX1 short #ss | 12 |
CE EA ss | JNX2 short #ss | 12 |
CE EB ss | JNX3 short #ss | 12 |
CE EC ss | JX0 short #ss | 12 |
CE ED ss | JX1 short #ss | 12 |
CE EE ss | JX2 short #ss | 12 |
CE EF ss | JX3 short #ss | 12 |
Flags Affected: None
RET = Return from routine
Hex | Mnemonic | Cycles |
---|---|---|
F8 | RET | 8 |
F9 | RETI | 8 |
FA | RETSKIP | 8 |
Flags Affected: None
System
HALT = Halt CPU
Hex | Mnemonic | Cycles |
---|---|---|
CE AE | HALT | 8 |
Flags Affected: None
STOP = Stop CPU
Hex | Mnemonic | Cycles |
---|---|---|
CE AF | STOP | 8 |
Flags Affected: None