Difference between revisions of "S1C88 InstructionSet"
From SublabWiki
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(→SRA: Arithmetic shift to right) |
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== '''SLL''': Logical shift to left == | == '''SLL''': Logical shift to left == | ||
== '''SRA''': Arithmetic shift to right == | == '''SRA''': Arithmetic shift to right == | ||
+ | {| class="wikitable sortable" | ||
+ | | [[S1C88_SRA|SRA]] | ||
+ | | A | ||
+ | | CE,88 | ||
+ | | ?PSEUDOCODE | ||
+ | | ?CYCLES | ||
+ | | 2 | ||
+ | | ?FLAGS | ||
+ | |- | ||
+ | | [[S1C88_SRA|SRA]] | ||
+ | | B | ||
+ | | CE,89 | ||
+ | | ?PSEUDOCODE | ||
+ | | ?CYCLES | ||
+ | | 2 | ||
+ | | ?FLAGS | ||
+ | |- | ||
+ | | [[S1C88_SRA|SRA]] | ||
+ | | [HL] | ||
+ | | CE,8B | ||
+ | | ?PSEUDOCODE | ||
+ | | ?CYCLES | ||
+ | | 2 | ||
+ | | ?FLAGS | ||
+ | |- | ||
+ | | [[S1C88_SRA|SRA]] | ||
+ | | [BR:ll] | ||
+ | | CE,8A,ll | ||
+ | | ?PSEUDOCODE | ||
+ | | ?CYCLES | ||
+ | | 3 | ||
+ | | ?FLAGS | ||
+ | |- | ||
+ | |} | ||
+ | |||
== '''SRL''': Logical shift to right == | == '''SRL''': Logical shift to right == | ||
Revision as of 23:49, 12 July 2015
THIS PAGE IS IN PROCESS
Contents
- 1 8-bit arithmetic and logic operation
- 1.1 ADD: Addition
- 1.2 ADC: Addition with carry
- 1.3 SUB: Subtraction
- 1.4 SBC: Subtraction with carry
- 1.5 AND: Logical product
- 1.6 OR: Logical sum
- 1.7 XOR: Exclusive OR
- 1.8 CP: Comparison
- 1.9 BIT: Bit test
- 1.10 INC: 1 increment
- 1.11 DEC: 1 decrement
- 1.12 MLT: Multiplication
- 1.13 DIV: Division
- 1.14 CPL: Complement of 1
- 1.15 NEG: Complement of 2
- 2 8-bit transfer
- 3 Rotate/shift
- 4 Auxiliary operation
- 5 16-bit arithmetic operation
- 6 16-bit transfer
- 7 Stack Control
- 8 Branch
- 9 System Control
- 10 Operation Code Map
- 11 Illegal Instructions
8-bit arithmetic and logic operation
ADD: Addition
ADC: Addition with carry
SUB: Subtraction
SUB | A,A | 10 | ?PSEUDOCODE | ?CYCLES | 1 | ?FLAGS |
A,B | 11 | ?PSEUDOCODE | ?CYCLES | 1 | ?FLAGS | |
A,#nn | 12,nn | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
A,[HL] | 13 | ?PSEUDOCODE | ?CYCLES | 1 | ?FLAGS | |
A,[BR:ll] | 14,ll | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
A,[hhll] | 15,ll,hh | ?PSEUDOCODE | ?CYCLES | 3 | ?FLAGS | |
A,[IX] | 16 | ?PSEUDOCODE | ?CYCLES | 1 | ?FLAGS | |
A,[IY] | 17 | ?PSEUDOCODE | ?CYCLES | 1 | ?FLAGS | |
A,[IX+dd] | CE,10,dd | ?PSEUDOCODE | ?CYCLES | 3 | ?FLAGS | |
A,[IY+dd] | CE,11,dd | ?PSEUDOCODE | ?CYCLES | 3 | ?FLAGS | |
A,[IX+L] | CE,12 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
A,[IY+L] | CE,13 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
SUB | IX,#mmnn | D2,nn,mm | ?PSEUDOCODE | ?CYCLES | 3 | ?FLAGS |
IX,BA | CE,48 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
IX,HL | CE,49 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
SUB | BA,#mmnn | D0,nn,mm | ?PSEUDOCODE | ?CYCLES | 3 | ?FLAGS |
BA,BA | CE, 8 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
BA,HL | CE, 9 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
BA,IX | CE, A | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
BA,IY | CE, B | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
SUB | SP,BA | CE,4C | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
SP,HL | CE,4D | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
SP,#mmnn | CE,6A,nn,mm | ?PSEUDOCODE | ?CYCLES | 4 | ?FLAGS | |
SUB | [HL],A | CE,14 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
[HL],#nn | CE,15,nn | ?PSEUDOCODE | ?CYCLES | 3 | ?FLAGS | |
[HL],[IX] | CE,16 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
[HL],[IY] | CE,17 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
SUB | IY,#mmnn | D3,nn,mm | ?PSEUDOCODE | ?CYCLES | 3 | ?FLAGS |
IY,BA | CE,4A | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
IY,HL | CE,4B | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
SUB | HL,#mmnn | D1,nn,mm | ?PSEUDOCODE | ?CYCLES | 3 | ?FLAGS |
HL,BA | CE,28 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
HL,HL | CE,29 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
HL,IX | CE,2A | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS | |
HL,IY | CE,2B | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
SBC: Subtraction with carry
AND: Logical product
OR: Logical sum
XOR: Exclusive OR
CP: Comparison
BIT: Bit test
INC: 1 increment
DEC: 1 decrement
MLT: Multiplication
DIV: Division
CPL: Complement of 1
CPL | A | CE,A0 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
CPL | B | CE,A1 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
CPL | [HL] | CE,A3 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
CPL | [BR:ll] | CE,A2,ll | ?PSEUDOCODE | ?CYCLES | 3 | ?FLAGS |
NEG: Complement of 2
NEG | A | CE,A4 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
NEG | B | CE,A5 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
NEG | [HL] | CE,A7 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
NEG | [BR:ll] | CE,A6,ll | ?PSEUDOCODE | ?CYCLES | 3 | ?FLAGS |
8-bit transfer
LD: Load
EX: Byte exchange
SWAP: Nibble exchange
Rotate/shift
RL: Rotate to left
RLC: Rotate to left with carry
RR: Rotate to right
RRC: Rotate to right with carry
SLA: Arithmetic shift to left
SLL: Logical shift to left
SRA: Arithmetic shift to right
SRA | A | CE,88 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
SRA | B | CE,89 | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
SRA | [HL] | CE,8B | ?PSEUDOCODE | ?CYCLES | 2 | ?FLAGS |
SRA | [BR:ll] | CE,8A,ll | ?PSEUDOCODE | ?CYCLES | 3 | ?FLAGS |
SRL: Logical shift to right
Auxiliary operation
PACK: Pack
UPCK: Unpack
SEP: Code extension
16-bit arithmetic operation
ADD: Addition
ADC: Addition with carry
SUB: Subtraction
SBC: Subtraction with carry
CP: Comparison
INC: 1 increment
DEC: 1 decrement
16-bit transfer
LD: Load
EX: Word exchange
Stack Control
PUSH: Push
POP: Pop
Branch
JRS: Relative short jump
JRL: Relative long jump
JP: Indirect jump
DJR: Loop
CARS: Relative short call
CARL: Relative long call
CALL: Indirect call
RET: Return
RETE: Exception processing return
RETS: Return and skip
INT: Software interrupt
System Control
NOP: No operation
HALT: Shifts to HALT status
SLP: Shifts to SLEEP status
Operation Code Map
1st operation code
x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | xA | xB | xC | xD | xE | xF | |
0x | ADD A,A | ADD A,B | ADD A,#nn | ADD A,[HL] | ADD A,[BR:ll] | ADD A,[hhll] | ADD A,[IX] | ADD A,[IY] | ADC A,A | ADC A,B | ADC A,#nn | ADC A,[HL] | ADC A,[BR:ll] | ADC A,[hhll] | ADC A,[IX] | ADC A,[IY] |
1x | SUB A,A | SUB A,B | SUB A,#nn | SUB A,[HL] | SUB A,[BR:ll] | SUB A,[hhll] | SUB A,[IX] | SUB A,[IY] | SBC A,A | SBC A,B | SBC A,#nn | SBC A,[HL] | SBC A,[BR:ll] | SBC A,[hhll] | SBC A,[IX] | SBC A,[IY] |
2x | AND A,A | AND A,B | AND A,#nn | AND A,[HL] | AND A,[BR:ll] | AND A,[hhll] | AND A,[IX] | AND A,[IY] | OR A,A | OR A,B | OR A,#nn | OR A,[HL] | OR A,[BR:ll] | OR A,[hhll] | OR A,[IX] | OR A,[IY] |
3x | CP A,A | CP A,B | CP A,#nn | CP A,[HL] | CP A,[BR:ll] | CP A,[hhll] | CP A,[IX] | CP A,[IY] | XOR A,A | XOR A,B | XOR A,#nn | XOR A,[HL] | XOR A,[BR:ll] | XOR A,[hhll] | XOR A,[IX] | XOR A,[IY] |
4x | LD A,A | LD A,B | LD A,L | LD A,H | LD A,[BR:ll] | LD A,[HL] | LD A,[IX] | LD A,[IY] | LD B,A | LD B,B | LD B,L | LD B,H | LD B,[BR:ll] | LD B,[HL] | LD B,[IX] | LD B,[IY] |
5x | LD L,A | LD L,B | LD L,L | LD L,H | LD L,[BR:ll] | LD L,[HL] | LD L,[IX] | LD L,[IY] | LD H,A | LD H,B | LD H,L | LD H,H | LD H,[BR:ll] | LD H,[HL] | LD H,[IX] | LD H,[IY] |
6x | LD [IX],A | LD [IX],B | LD [IX],L | LD [IX],H | LD [IX],[BR:ll] | LD [IX],[HL] | LD [IX],[IX] | LD [IX],[IY] | LD [HL],A | LD [HL],B | LD [HL],L | LD [HL],H | LD [HL],[BR:ll] | LD [HL],[HL] | LD [HL],[IX] | LD [HL],[IY] |
7x | LD [IY],A | LD [IY],B | LD [IY],L | LD [IY],H | LD [IY],[BR:ll] | LD [IY],[HL] | LD [IY],[IX] | LD [IY],[IY] | LD [BR:ll],A | LD [BR:ll],B | LD [BR:ll],L | LD [BR:ll],H | LD [BR:ll],[HL] | LD [BR:ll],[IX] | LD [BR:ll],[IY] | |
8x | INC A | INC B | INC L | INC H | INC BR | INC [BR:ll] | INC [HL] | INC SP | DEC A | DEC B | DEC L | DEC H | DEC BR | DEC [BR:ll] | DEC [HL] | DEC SP |
9x | INC BA | INC HL | INC IX | INC IY | BIT A,B | BIT [HL],#nn | BIT A,#nn | BIT B,#nn | DEC BA | DEC HL | DEC IX | DEC IY | AND SC,#nn | OR SC,#nn | XOR SC,#nn | LD SC,#nn |
Ax | PUSH BA | PUSH HL | PUSH IX | PUSH IY | PUSH BR | PUSH EP | PUSH IP | PUSH SC | POP BA | POP HL | POP IX | POP IY | POP BR | POP EP | POP IP | POP SC |
Bx | LD A,#nn | LD B,#nn | LD L,#nn | LD H,#nn | LD BR,#hh | LD [HL],#nn | LD [IX],#nn | LD [IY],#nn | LD BA,[hhll] | LD HL,[hhll] | LD IX,[hhll] | LD IY,[hhll] | LD [hhll],BA | LD [hhll],HL | LD [hhll],IX | LD [hhll],IY |
Cx | ADD BA,#mmnn | ADD HL,#mmnn | ADD IX,#mmnn | ADD IY,#mmnn | LD BA,#mmnn | LD HL,#mmnn | LD IX,#mmnn | LD IY,#mmnn | EX BA,HL | EX BA,IX | EX BA,IY | EX BA,SP | EX A,B | EX A,[HL] | Expansion Code | Expansion Code |
Dx | SUB BA,#mmnn | SUB HL,#mmnn | SUB IX,#mmnn | SUB IY,#mmnn | CP BA,#mmnn | CP HL,#mmnn | CP IX,#mmnn | CP IY,#mmnn | AND [BR:ll],#nn | OR [BR:ll],#nn | XOR [BR:ll],#nn | CP [BR:ll],#nn | BIT [BR:ll],#nn | LD [BR:ll],#nn | PACK | UPCK |
Ex | CARS C,rr | CARS NC,rr | CARS Z,rr | CARS NZ,rr | JRS C,rr | JRS NC,rr | JRS Z,rr | JRS NZ,rr | CARL C,qqrr | CARL NC,qqrr | CARL Z,qqrr | CARL NZ,qqrr | JRL C,qqrr | JRL NC,qqrr | JRL Z,qqrr | JRL NZ,qqrr |
Fx | CARS rr | JRS rr | CARL qqrr | JRL qqrr | JP HL | DJR NZ,rr | SWAP A | SWAP [HL] | RET | RETE | RETS | CALL [hhll] | INT [kk] | JP [kk] | NOP |
2nd operation code (1st operation code = CE)
x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | xA | xB | xC | xD | xE | xF | |
0x | ADD A,[IX+dd] | ADD A,[IY+dd] | ADD A,[IX+L] | ADD A,[IY+L] | ADD [HL],A | ADD [HL],#nn | ADD [HL],[IX] | ADD [HL],[IY] | ADC A,[IX+dd] | ADC A,[IY+dd] | ADC A,[IX+L] | ADC A,[IY+L] | ADC [HL],A | ADC [HL],#nn | ADC [HL],[IX] | ADC [HL],[IY] |
1x | SUB A,[IX+dd] | SUB A,[IY+dd] | SUB A,[IX+L] | SUB A,[IY+L] | SUB [HL],A | SUB [HL],#nn | SUB [HL],[IX] | SUB [HL],[IY] | SBC A,[IX+dd] | SBC A,[IY+dd] | SBC A,[IX+L] | SBC A,[IY+L] | SBC [HL],A | SBC [HL],#nn | SBC [HL],[IX] | SBC [HL],[IY] |
2x | AND A,[IX+dd] | AND A,[IY+dd] | AND A,[IX+L] | AND A,[IY+L] | AND [HL],A | AND [HL],#nn | AND [HL],[IX] | AND [HL],[IY] | OR A,[IX+dd] | OR A,[IY+dd] | OR A,[IX+L] | OR A,[IY+L] | OR [HL],A | OR [HL],#nn | OR [HL],[IX] | OR [HL],[IY] |
3x | CP A,[IX+dd] | CP A,[IY+dd] | CP A,[IX+L] | CP A,[IY+L] | CP [HL],A | CP [HL],#nn | CP [HL],[IX] | CP [HL],[IY] | XOR A,[IX+dd] | XOR A,[IY+dd] | XOR A,[IX+L] | XOR A,[IY+L] | XOR [HL],A | XOR [HL],#nn | XOR [HL],[IX] | XOR [HL],[IY] |
4x | LD A,[IX+dd] | LD A,[IY+dd] | LD A,[IX+L] | LD A,[IY+L] | LD [IX+dd],A | LD [IY+dd],A | LD [IX+L],A | LD [IY+L],A | LD B,[IX+dd] | LD B,[IY+dd] | LD B,[IX+L] | LD B,[IY+L] | LD [IX+dd],B | LD [IY+dd],B | LD [IX+L],B | LD [IY+L],B |
5x | LD L,[IX+dd] | LD L,[IY+dd] | LD L,[IX+L] | LD L,[IY+L] | LD [IX+dd],L | LD [IY+dd],L | LD [IX+L],L | LD [IY+L],L | LD H,[IX+dd] | LD H,[IY+dd] | LD H,[IX+L] | LD H,[IY+L] | LD [IX+dd],H | LD [IY+dd],H | LD [IX+L],H | LD [IY+L],H |
6x | LD [HL],[IX+dd] | LD [HL],[IY+dd] | LD [HL],[IX+L] | LD [HL],[IY+L] | LD [IX],[IX+dd] | LD [IX],[IY+dd] | LD [IX],[IX+L] | LD [IX],[IY+L] | ||||||||
7x | LD [IY],[IX+dd] | LD [IY],[IY+dd] | LD [IY],[IX+L] | LD [IY],[IY+L] | ||||||||||||
8x | SLA A | SLA B | SLA [BR:ll] | SLA [HL] | SLL A | SLL B | SLL [BR:ll] | SLL [HL] | SRA A | SRA B | SRA [BR:ll] | SRA [HL] | SRL A | SRL B | SRL [BR:ll] | SRL [HL] |
9x | RL A | RL B | RL [BR:ll] | RL [HL] | RLC A | RLC B | RLC [BR:ll] | RLC [HL] | RR A | RR B | RR [BR:ll] | RR [HL] | RRC A | RRC B | RRC [BR:ll] | RRC [HL] |
Ax | CPL A | CPL B | CPL [BR:ll] | CPL [HL] | NEG A | NEG B | NEG [BR:ll] | NEG [HL] | SEP | HALT | SLP | |||||
Bx | AND B,#nn | AND L,#nn | AND H,#nn | OR B,#nn | OR L,#nn | OR H,#nn | XOR B,#nn | XOR L,#nn | XOR H,#nn | CP B,#nn | CP L,#nn | CP H,#nn | CP BR,#hh | |||
Cx | LD A,BR | LD A,SC | LD BR,A | LD SC,A | LD NB,#bb | LD EP,#pp | LD XP,#pp | LD YP,#pp | LD A,NB | LD A,EP | LD A,XP | LD A,YP | LD NB,A | LD EP,A | LD XP,A | LD YP,A |
Dx | LD A,[hhll] | LD B,[hhll] | LD L,[hhll] | LD H,[hhll] | LD [hhll],A | LD [hhll],B | LD [hhll],L | LD [hhll],H | MLT | DIV | ||||||
Ex | JRS LT,rr | JRS LE,rr | JRS GT,rr | JRS GE,rr | JRS V,rr | JRS NV,rr | JRS P,rr | JRS M,rr | JRS F0,rr | JRS F1,rr | JRS F2,rr | JRS F3,rr | JRS NF0,rr | JRS NF1,rr | JRS NF2,rr | JRS NF3,rr |
Fx | CARS LT,rr | CARS LE,rr | CARS GT,rr | CARS GE,rr | CARS V,rr | CARS NV,rr | CARS P,rr | CARS M,rr | CARS F0,rr | CARS F1,rr | CARS F2,rr | CARS F3,rr | CARS NF0,rr | CARS NF1,rr | CARS NF2,rr | CARS NF3,rr |
3nd operation code (1st operation code = CF)
x0 | x1 | x2 | x3 | x4 | x5 | x6 | x7 | x8 | x9 | xA | xB | xC | xD | xE | xF | |
0x | ADD BA,BA | ADD BA,HL | ADD BA,IX | ADD BA,IY | ADC BA,BA | ADC BA,HL | ADC BA,IX | ADC BA,IY | SUB BA,BA | SUB BA,HL | SUB BA,IX | SUB BA,IY | SBC BA,BA | SBC BA,HL | SBC BA,IX | SBC BA,IY |
1x | CP BA,BA | CP BA,HL | CP BA,IX | CP BA,IY | ||||||||||||
2x | ADD HL,BA | ADD HL,HL | ADD HL,IX | ADD HL,IY | ADC HL,BA | ADC HL,HL | ADC HL,IX | ADC HL,IY | SUB HL,BA | SUB HL,HL | SUB HL,IX | SUB HL,IY | SBC HL,BA | SBC HL,HL | SBC HL,IX | SBC HL,IY |
3x | CP HL,BA | CP HL,HL | CP HL,IX | CP HL,IY | ||||||||||||
4x | ADD IX,BA | ADD IX,HL | ADD IY,BA | ADD IY,HL | ADD SP,BA | ADD SP,HL | SUB IX,BA | SUB IX,HL | SUB IY,BA | SUB IY,HL | SUB SP,BA | SUB SP,HL | ||||
5x | CP SP,BA | CP SP,HL | ||||||||||||||
6x | ADC BA,#mmnn | ADC HL,#mmnn | SBC BA,#mmnn | SBC HL,#mmnn | ADD SP,#mmnn | SUB SP,#mmnn | CP SP,#mmnn | LD SP,#mmnn | ||||||||
7x | LD BA,[SP+dd] | LD HL,[SP+dd] | LD IX,[SP+dd] | LD IY,[SP+dd] | LD [SP+dd],BA | LD [SP+dd],HL | LD [SP+dd],IX | LD [SP+dd],IY | LD SP,[hhll] | LD [hhll],SP | ||||||
8x | ||||||||||||||||
9x | ||||||||||||||||
Ax | ||||||||||||||||
Bx | PUSH A | PUSH B | PUSH L | PUSH H | POP A | POP B | POP L | POP H | PUSH ALL | PUSH ALE | POP ALL | POP ALE | ||||
Cx | LD BA,[HL] | LD HL,[HL] | LD IX,[HL] | LD IY,[HL] | LD [HL],BA | LD [HL],HL | LD [HL],IX | LD [HL],IY | ||||||||
Dx | LD BA,[IX] | LD HL,[IX] | LD IX,[IX] | LD IY,[IX] | LD [IX],BA | LD [IX],HL | LD [IX],IX | LD [IX],IY | LD BA,[IY] | LD HL,[IY] | LD IX,[IY] | LD IY,[IY] | LD [IY],BA | LD [IY],HL | LD [IY],IX | LD [IY],IY |
Ex | LD BA,BA | LD BA,HL | LD BA,IX | LD BA,IY | LD HL,BA | LD HL,HL | LD HL,IX | LD HL,IY | LD IX,BA | LD IX,HL | LD IX,IX | LD IX,IY | LD IY,BA | LD IY,HL | LD IY,IX | LD IY,IY |
Fx | LD SP,BA | LD SP,HL | LD SP,IX | LD SP,IY | LD HL,SP | LD HL,PC | LD BA,SP | LD BA,PC | LD IX,SP | LD IY,SP |
Illegal Instructions
NOTE: This document is now out of date, as should be updated to the new mnemonic and register naming
The entire opcode table has been evaluated on Pokemon Mini units and new and exotic illegal opcodes have been found.
These opcodes are not officially supported (they are not used by commercial games and not even found in the Pokemon Channel emulator) and can produce random results or crashes in some cases. The illegal opcodes have been documented on this page's Discussion page.