Difference between revisions of "S1C88 InstructionSet"

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m (Asterick moved page PM InstructionList to S1C88 InstructionSet: Core discovered)
(Starting to move to S1C88 naming)
Line 1: Line 1:
= Move =
+
= 8-bit arithmetic and logic operation =
 +
== ''ADD'' Addition ==
 +
== ''ADC'' Addition with carry ==
 +
== ''SUB'' Subtraction ==
 +
== ''SBC'' Subtraction with carry ==
 +
== ''AND'' Logical product ==
 +
== ''OR'' Logical sum ==
 +
== ''XOR'' Exclusive OR ==
 +
== ''CP'' Comparison ==
 +
== ''BIT'' Bit test ==
 +
== ''INC'' 1 increment ==
 +
== ''DEC'' 1 decrement ==
 +
== ''MLT'' Multiplication ==
 +
== ''DIV'' Division ==
 +
== ''CPL'' Complement of 1 ==
 +
== ''NEG'' Complement of 2 ==
  
== NOP = No Operation ==
+
= 8-bit transfer =
 +
== ''LD'' Load ==
 +
== ''EX'' Byte exchange ==
 +
== ''SWAP'' Nibble exchange ==
  
{| border="1" style="text-align:left" class="sortable"
+
= Rotate/shift =
!Hex
+
== ''RL'' Rotate to left ==
!Mnemonic
+
== ''RLC'' Rotate to left with carry ==
!Cycles
+
== ''RR'' Rotate to right ==
|-
+
== ''RRC'' Rotate to right with carry ==
|FF
+
== ''SLA'' Arithmetic shift to left ==
|[[PM_Opc_NOP|NOP]]
+
== ''SLL'' Logical shift to left ==
|8
+
== ''SRA'' Arithmetic shift to right ==
|}
+
== ''SRL'' Logical shift to right ==
  
'''Flags Affected:''' None
+
= Auxiliary operation =
 +
== ''PACK'' Pack ==
 +
== ''UPCK'' Unpack ==
 +
== ''SEP'' Code extension ==
  
== MOV = Move Register ==
+
= 16-bit arithmetic operation =
 +
== ''ADD'' Addition ==
 +
== ''ADC'' Addition with carry ==
 +
== ''SUB'' Subtraction ==
 +
== ''SBC'' Subtraction with carry ==
 +
== ''CP'' Comparison ==
 +
== ''INC'' 1 increment ==
 +
== ''DEC'' 1 decrement ==
  
[[PM_Opc_MOV8|8 Bit Opcode overview]]
+
= 16-bit transfer =
 +
== ''LD'' Load ==
 +
== ''EX'' Word exchange ==
  
[[PM_Opc_MOV16|16 Bit Opcode overview]]
+
= Stack Control =
 
+
== ''PUSH'' Push ==
{| border="1" style="text-align:left" class="sortable"
+
== ''POP'' Pop ==
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|40
 
|[[PM_Opc_MOV8|MOV A, A]]
 
|4
 
|-
 
|41
 
|[[PM_Opc_MOV8|MOV A, B]]
 
|4
 
|-
 
|42
 
|[[PM_Opc_MOV8|MOV A, L]]
 
|4
 
|-
 
|43
 
|[[PM_Opc_MOV8|MOV A, H]]
 
|4
 
|-
 
|44 nn
 
|[[PM_Opc_MOV8|MOV A, [N+#nn]]]
 
|12
 
|-
 
|45
 
|[[PM_Opc_MOV8|MOV A, [HL]]]
 
|8
 
|-
 
|46
 
|[[PM_Opc_MOV8|MOV A, [X]]]
 
|8
 
|-
 
|47
 
|[[PM_Opc_MOV8|MOV A, [Y]]]
 
|8
 
|-
 
|48
 
|[[PM_Opc_MOV8|MOV B, A]]
 
|4
 
|-
 
|49
 
|[[PM_Opc_MOV8|MOV B, B]]
 
|4
 
|-
 
|4A
 
|[[PM_Opc_MOV8|MOV B, L]]
 
|4
 
|-
 
|4B
 
|[[PM_Opc_MOV8|MOV B, H]]
 
|4
 
|-
 
|4C nn
 
|[[PM_Opc_MOV8|MOV B, [N+#nn]]]
 
|12
 
|-
 
|4D
 
|[[PM_Opc_MOV8|MOV B, [HL]]]
 
|8
 
|-
 
|4E
 
|[[PM_Opc_MOV8|MOV B, [X]]]
 
|8
 
|-
 
|4F
 
|[[PM_Opc_MOV8|MOV B, [Y]]]
 
|8
 
|-
 
|50
 
|[[PM_Opc_MOV8|MOV L, A]]
 
|4
 
|-
 
|51
 
|[[PM_Opc_MOV8|MOV L, B]]
 
|4
 
|-
 
|52
 
|[[PM_Opc_MOV8|MOV L, L]]
 
|4
 
|-
 
|53
 
|[[PM_Opc_MOV8|MOV L, H]]
 
|4
 
|-
 
|54 nn
 
|[[PM_Opc_MOV8|MOV L, [N+#nn]]]
 
|12
 
|-
 
|55
 
|[[PM_Opc_MOV8|MOV L, [HL]]]
 
|8
 
|-
 
|56
 
|[[PM_Opc_MOV8|MOV L, [X]]]
 
|8
 
|-
 
|57
 
|[[PM_Opc_MOV8|MOV L, [Y]]]
 
|8
 
|-
 
|58
 
|[[PM_Opc_MOV8|MOV H, A]]
 
|4
 
|-
 
|59
 
|[[PM_Opc_MOV8|MOV H, B]]
 
|4
 
|-
 
|5A
 
|[[PM_Opc_MOV8|MOV H, L]]
 
|4
 
|-
 
|5B
 
|[[PM_Opc_MOV8|MOV H, H]]
 
|4
 
|-
 
|5C nn
 
|[[PM_Opc_MOV8|MOV H, [N+#nn]]]
 
|12
 
|-
 
|5D
 
|[[PM_Opc_MOV8|MOV H, [HL]]]
 
|8
 
|-
 
|5E
 
|[[PM_Opc_MOV8|MOV H, [X]]]
 
|8
 
|-
 
|5F
 
|[[PM_Opc_MOV8|MOV H, [Y]]]
 
|8
 
|-
 
|60
 
|[[PM_Opc_MOV8|MOV [X], A]]
 
|8
 
|-
 
|61
 
|[[PM_Opc_MOV8|MOV [X], B]]
 
|8
 
|-
 
|62
 
|[[PM_Opc_MOV8|MOV [X], L]]
 
|8
 
|-
 
|63
 
|[[PM_Opc_MOV8|MOV [X], H]]
 
|8
 
|-
 
|64 nn
 
|[[PM_Opc_MOV8|MOV [X], [N+#nn]]]
 
|16
 
|-
 
|65
 
|[[PM_Opc_MOV8|MOV [X], [HL]]]
 
|12
 
|-
 
|66
 
|[[PM_Opc_MOV8|MOV [X], [X]]]
 
|12
 
|-
 
|67
 
|[[PM_Opc_MOV8|MOV [X], [Y]]]
 
|12
 
|-
 
|68
 
|[[PM_Opc_MOV8|MOV [HL], A]]
 
|8
 
|-
 
|69
 
|[[PM_Opc_MOV8|MOV [HL], B]]
 
|8
 
|-
 
|6A
 
|[[PM_Opc_MOV8|MOV [HL], L]]
 
|8
 
|-
 
|6B
 
|[[PM_Opc_MOV8|MOV [HL], H]]
 
|8
 
|-
 
|6C nn
 
|[[PM_Opc_MOV8|MOV [HL], [N+#nn]]]
 
|16
 
|-
 
|6D
 
|[[PM_Opc_MOV8|MOV [HL], [HL]]]
 
|12
 
|-
 
|6E
 
|[[PM_Opc_MOV8|MOV [HL], [X]]]
 
|12
 
|-
 
|6F
 
|[[PM_Opc_MOV8|MOV [HL], [Y]]]
 
|12
 
|-
 
|70
 
|[[PM_Opc_MOV8|MOV [Y], A]]
 
|8
 
|-
 
|71
 
|[[PM_Opc_MOV8|MOV [Y], B]]
 
|8
 
|-
 
|72
 
|[[PM_Opc_MOV8|MOV [Y], L]]
 
|8
 
|-
 
|73
 
|[[PM_Opc_MOV8|MOV [Y], H]]
 
|8
 
|-
 
|74 nn
 
|[[PM_Opc_MOV8|MOV [Y], [N+#nn]]]
 
|16
 
|-
 
|75
 
|[[PM_Opc_MOV8|MOV [Y], [HL]]]
 
|12
 
|-
 
|76
 
|[[PM_Opc_MOV8|MOV [Y], [X]]]
 
|12
 
|-
 
|77
 
|[[PM_Opc_MOV8|MOV [Y], [Y]]]
 
|12
 
|-
 
|78 nn
 
|[[PM_Opc_MOV8|MOV [N+#nn], A]]
 
|12
 
|-
 
|79 nn
 
|[[PM_Opc_MOV8|MOV [N+#nn], B]]
 
|12
 
|-
 
|7A nn
 
|[[PM_Opc_MOV8|MOV [N+#nn], L]]
 
|12
 
|-
 
|7B nn
 
|[[PM_Opc_MOV8|MOV [N+#nn], H]]
 
|12
 
|-
 
|7D nn
 
|[[PM_Opc_MOV8|MOV [N+#nn], [HL]]]
 
|16
 
|-
 
|7E nn
 
|[[PM_Opc_MOV8|MOV [N+#nn], [X]]]
 
|16
 
|-
 
|7F nn
 
|[[PM_Opc_MOV8|MOV [N+#nn], [Y]]]
 
|16
 
|-
 
|9F nn
 
|[[PM_Opc_MOV8|MOV F, #nn]]
 
|12
 
|-
 
|B0 nn
 
|[[PM_Opc_MOV8|MOV A, #nn]]
 
|8
 
|-
 
|B1 nn
 
|[[PM_Opc_MOV8|MOV B, #nn]]
 
|8
 
|-
 
|B2 nn
 
|[[PM_Opc_MOV8|MOV L, #nn]]
 
|8
 
|-
 
|B3 nn
 
|[[PM_Opc_MOV8|MOV H, #nn]]
 
|8
 
|-
 
|B4 nn
 
|[[PM_Opc_MOV8|MOV N, #nn]]
 
|8
 
|-
 
|B5 nn
 
|[[PM_Opc_MOV8|MOV [HL], #nn]]
 
|12
 
|-
 
|B6 nn
 
|[[PM_Opc_MOV8|MOV [X], #nn]]
 
|12
 
|-
 
|B7 nn
 
|[[PM_Opc_MOV8|MOV [Y], #nn]]
 
|12
 
|-
 
|DD nn nn
 
|[[PM_Opc_MOV8|MOV [N+#nn], #nn]]
 
|16
 
|-
 
|CE C4 nn
 
|[[PM_Opc_MOV8|MOV U, #nn]]
 
|16
 
|-
 
|CE C5 nn
 
|[[PM_Opc_MOV8|MOV I, #nn]]
 
|12
 
|-
 
|CE C6 nn
 
|[[PM_Opc_MOV8|MOV XI, #nn]]
 
|12
 
|-
 
|CE C7 nn
 
|[[PM_Opc_MOV8|MOV YI, #nn]]
 
|12
 
|-
 
|CE 40 ss
 
|[[PM_Opc_MOV8|MOV A, [X+#ss]]]
 
|16
 
|-
 
|CE 41 ss
 
|[[PM_Opc_MOV8|MOV A, [Y+#ss]]]
 
|16
 
|-
 
|CE 42
 
|[[PM_Opc_MOV8|MOV A, [X+L]]]
 
|16
 
|-
 
|CE 43
 
|[[PM_Opc_MOV8|MOV A, [Y+L]]]
 
|16
 
|-
 
|CE 48 ss
 
|[[PM_Opc_MOV8|MOV B, [X+#ss]]]
 
|16
 
|-
 
|CE 49 ss
 
|[[PM_Opc_MOV8|MOV B, [Y+#ss]]]
 
|16
 
|-
 
|CE 4A
 
|[[PM_Opc_MOV8|MOV B, [X+L]]]
 
|16
 
|-
 
|CE 4B
 
|[[PM_Opc_MOV8|MOV B, [Y+L]]]
 
|16
 
|-
 
|CE 50 ss
 
|[[PM_Opc_MOV8|MOV L, [X+#ss]]]
 
|16
 
|-
 
|CE 51 ss
 
|[[PM_Opc_MOV8|MOV L, [Y+#ss]]]
 
|16
 
|-
 
|CE 52
 
|[[PM_Opc_MOV8|MOV L, [X+L]]]
 
|16
 
|-
 
|CE 53
 
|[[PM_Opc_MOV8|MOV L, [Y+L]]]
 
|16
 
|-
 
|CE 58 ss
 
|[[PM_Opc_MOV8|MOV H, [X+#ss]]]
 
|16
 
|-
 
|CE 59 ss
 
|[[PM_Opc_MOV8|MOV H, [Y+#ss]]]
 
|16
 
|-
 
|CE 5A
 
|[[PM_Opc_MOV8|MOV H, [X+L]]]
 
|16
 
|-
 
|CE 5B
 
|[[PM_Opc_MOV8|MOV H, [Y+L]]]
 
|16
 
|-
 
|CE 44 ss
 
|[[PM_Opc_MOV8|MOV [X+#ss], A]]
 
|16
 
|-
 
|CE 45 ss
 
|[[PM_Opc_MOV8|MOV [Y+#ss], A]]
 
|16
 
|-
 
|CE 46
 
|[[PM_Opc_MOV8|MOV [X+L], A]]
 
|16
 
|-
 
|CE 47
 
|[[PM_Opc_MOV8|MOV [Y+L], A]]
 
|16
 
|-
 
|CE 4C ss
 
|[[PM_Opc_MOV8|MOV [X+#ss], B]]
 
|16
 
|-
 
|CE 4D ss
 
|[[PM_Opc_MOV8|MOV [Y+#ss], B]]
 
|16
 
|-
 
|CE 4E
 
|[[PM_Opc_MOV8|MOV [X+L], B]]
 
|16
 
|-
 
|CE 4F
 
|[[PM_Opc_MOV8|MOV [Y+L], B]]
 
|16
 
|-
 
|CE 54 ss
 
|[[PM_Opc_MOV8|MOV [X+#ss], L]]
 
|16
 
|-
 
|CE 55 ss
 
|[[PM_Opc_MOV8|MOV [Y+#ss], L]]
 
|16
 
|-
 
|CE 56
 
|[[PM_Opc_MOV8|MOV [X+L], L]]
 
|16
 
|-
 
|CE 57
 
|[[PM_Opc_MOV8|MOV [Y+L], L]]
 
|16
 
|-
 
|CE 5C ss
 
|[[PM_Opc_MOV8|MOV [X+#ss], H]]
 
|16
 
|-
 
|CE 5D ss
 
|[[PM_Opc_MOV8|MOV [Y+#ss], H]]
 
|16
 
|-
 
|CE 5E
 
|[[PM_Opc_MOV8|MOV [X+L], H]]
 
|16
 
|-
 
|CE 5F
 
|[[PM_Opc_MOV8|MOV [Y+L], H]]
 
|16
 
|-
 
|CE 60 ss
 
|[[PM_Opc_MOV8|MOV [HL], [X+#ss]]]
 
|20
 
|-
 
|CE 61 ss
 
|[[PM_Opc_MOV8|MOV [HL], [Y+#ss]]]
 
|20
 
|-
 
|CE 62
 
|[[PM_Opc_MOV8|MOV [HL], [X+L]]]
 
|20
 
|-
 
|CE 63
 
|[[PM_Opc_MOV8|MOV [HL], [Y+L]]]
 
|20
 
|-
 
|CE 68 ss
 
|[[PM_Opc_MOV8|MOV [X], [X+#ss]]]
 
|20
 
|-
 
|CE 69 ss
 
|[[PM_Opc_MOV8|MOV [X], [Y+#ss]]]
 
|20
 
|-
 
|CE 6A
 
|[[PM_Opc_MOV8|MOV [X], [X+L]]]
 
|20
 
|-
 
|CE 6B
 
|[[PM_Opc_MOV8|MOV [X], [Y+L]]]
 
|20
 
|-
 
|CE 78 ss
 
|[[PM_Opc_MOV8|MOV [Y], [X+#ss]]]
 
|20
 
|-
 
|CE 79 ss
 
|[[PM_Opc_MOV8|MOV [Y], [Y+#ss]]]
 
|20
 
|-
 
|CE 7A
 
|[[PM_Opc_MOV8|MOV [Y], [X+L]]]
 
|20
 
|-
 
|CE 7B
 
|[[PM_Opc_MOV8|MOV [Y], [Y+L]]]
 
|20
 
|-
 
|B8 nn nn
 
|[[PM_Opc_MOV16|MOV BA, [#nnnn]]]
 
|20
 
|-
 
|B9 nn nn
 
|[[PM_Opc_MOV16|MOV HL, [#nnnn]]]
 
|20
 
|-
 
|BA nn nn
 
|[[PM_Opc_MOV16|MOV X, [#nnnn]]]
 
|20
 
|-
 
|BB nn nn
 
|[[PM_Opc_MOV16|MOV Y, [#nnnn]]]
 
|20
 
|-
 
|CF 78 nn nn
 
|[[PM_Opc_MOV16|MOV SP, [#nnnn]]]
 
|24
 
|-
 
|BC nn nn
 
|[[PM_Opc_MOV16|MOV [#nnnn], BA]]
 
|20
 
|-
 
|BD nn nn
 
|[[PM_Opc_MOV16|MOV [#nnnn], HL]]
 
|20
 
|-
 
|BE nn nn
 
|[[PM_Opc_MOV16|MOV [#nnnn], X]]
 
|20
 
|-
 
|BF nn nn
 
|[[PM_Opc_MOV16|MOV [#nnnn], Y]]
 
|20
 
|-
 
|CF 7C nn nn
 
|[[PM_Opc_MOV16|MOV [#nnnn], SP]]
 
|24
 
|-
 
|C4 nn nn
 
|[[PM_Opc_MOV16|MOV BA, #nnnn]]
 
|12
 
|-
 
|C5 nn nn
 
|[[PM_Opc_MOV16|MOV HL, #nnnn]]
 
|12
 
|-
 
|C6 nn nn
 
|[[PM_Opc_MOV16|MOV X, #nnnn]]
 
|12
 
|-
 
|C7 nn nn
 
|[[PM_Opc_MOV16|MOV Y, #nnnn]]
 
|12
 
|-
 
|CF 6E nn nn
 
|[[PM_Opc_MOV16|MOV SP, #nnnn]]
 
|16
 
|-
 
|CE C0
 
|[[PM_Opc_MOV8|MOV A, N]]
 
|8
 
|-
 
|CE C1
 
|[[PM_Opc_MOV8|MOV A, F]]
 
|8
 
|-
 
|CE C8
 
|[[PM_Opc_MOV8|MOV A, V]]
 
|8
 
|-
 
|CE C9
 
|[[PM_Opc_MOV8|MOV A, I]]
 
|8
 
|-
 
|CE CA
 
|[[PM_Opc_MOV8|MOV A, XI]]
 
|8
 
|-
 
|CE CB
 
|[[PM_Opc_MOV8|MOV A, YI]]
 
|8
 
|-
 
|CE C2
 
|[[PM_Opc_MOV8|MOV N, A]]
 
|8
 
|-
 
|CE C3
 
|[[PM_Opc_MOV8|MOV F, A]]
 
|12
 
|-
 
|CE CC
 
|[[PM_Opc_MOV8|MOV U, A]]
 
|12
 
|-
 
|CE CD
 
|[[PM_Opc_MOV8|MOV I, A]]
 
|8
 
|-
 
|CE CE
 
|[[PM_Opc_MOV8|MOV XI, A]]
 
|8
 
|-
 
|CE CF
 
|[[PM_Opc_MOV8|MOV YI, A]]
 
|8
 
|-
 
|CE D0 nn nn
 
|[[PM_Opc_MOV8|MOV A, [#nnnn]]]
 
|20
 
|-
 
|CE D1 nn nn
 
|[[PM_Opc_MOV8|MOV B, [#nnnn]]]
 
|20
 
|-
 
|CE D2 nn nn
 
|[[PM_Opc_MOV8|MOV L, [#nnnn]]]
 
|20
 
|-
 
|CE D3 nn nn
 
|[[PM_Opc_MOV8|MOV H, [#nnnn]]]
 
|20
 
|-
 
|CE D4 nn nn
 
|[[PM_Opc_MOV8|MOV [#nnnn], A]]
 
|20
 
|-
 
|CE D5 nn nn
 
|[[PM_Opc_MOV8|MOV [#nnnn], B]]
 
|20
 
|-
 
|CE D6 nn nn
 
|[[PM_Opc_MOV8|MOV [#nnnn], L]]
 
|20
 
|-
 
|CE D7 nn nn
 
|[[PM_Opc_MOV8|MOV [#nnnn], H]]
 
|20
 
|-
 
|CF 70 ss
 
|[[PM_Opc_MOV16|MOV BA, [SP+#ss]]]
 
|24
 
|-
 
|CF 71 ss
 
|[[PM_Opc_MOV16|MOV HL, [SP+#ss]]]
 
|24
 
|-
 
|CF 72 ss
 
|[[PM_Opc_MOV16|MOV X, [SP+#ss]]]
 
|24
 
|-
 
|CF 73 ss
 
|[[PM_Opc_MOV16|MOV Y, [SP+#ss]]]
 
|24
 
|-
 
|CF 74 ss
 
|[[PM_Opc_MOV16|MOV [SP+#ss], BA]]
 
|24
 
|-
 
|CF 75 ss
 
|[[PM_Opc_MOV16|MOV [SP+#ss], HL]]
 
|24
 
|-
 
|CF 76 ss
 
|[[PM_Opc_MOV16|MOV [SP+#ss], X]]
 
|24
 
|-
 
|CF 77 ss
 
|[[PM_Opc_MOV16|MOV [SP+#ss], Y]]
 
|24
 
|-
 
|CF C0
 
|[[PM_Opc_MOV16|MOV BA, [HL]]]
 
|20
 
|-
 
|CF C1
 
|[[PM_Opc_MOV16|MOV HL, [HL]]]
 
|20
 
|-
 
|CF C2
 
|[[PM_Opc_MOV16|MOV X, [HL]]]
 
|20
 
|-
 
|CF C3
 
|[[PM_Opc_MOV16|MOV Y, [HL]]]
 
|20
 
|-
 
|CF D0
 
|[[PM_Opc_MOV16|MOV BA, [X]]]
 
|20
 
|-
 
|CF D1
 
|[[PM_Opc_MOV16|MOV HL, [X]]]
 
|20
 
|-
 
|CF D2
 
|[[PM_Opc_MOV16|MOV X, [X]]]
 
|20
 
|-
 
|CF D3
 
|[[PM_Opc_MOV16|MOV Y, [X]]]
 
|20
 
|-
 
|CF D8
 
|[[PM_Opc_MOV16|MOV BA, [Y]]]
 
|20
 
|-
 
|CF D9
 
|[[PM_Opc_MOV16|MOV HL, [Y]]]
 
|20
 
|-
 
|CF DA
 
|[[PM_Opc_MOV16|MOV X, [Y]]]
 
|20
 
|-
 
|CF DB
 
|[[PM_Opc_MOV16|MOV Y, [Y]]]
 
|20
 
|-
 
|CF C4
 
|[[PM_Opc_MOV16|MOV [HL], BA]]
 
|20
 
|-
 
|CF C5
 
|[[PM_Opc_MOV16|MOV [HL], HL]]
 
|20
 
|-
 
|CF C6
 
|[[PM_Opc_MOV16|MOV [HL], X]]
 
|20
 
|-
 
|CF C7
 
|[[PM_Opc_MOV16|MOV [HL], Y]]
 
|20
 
|-
 
|CF D4
 
|[[PM_Opc_MOV16|MOV [X], BA]]
 
|20
 
|-
 
|CF D5
 
|[[PM_Opc_MOV16|MOV [X], HL]]
 
|20
 
|-
 
|CF D6
 
|[[PM_Opc_MOV16|MOV [X], X]]
 
|20
 
|-
 
|CF D7
 
|[[PM_Opc_MOV16|MOV [X], Y]]
 
|20
 
|-
 
|CF DC
 
|[[PM_Opc_MOV16|MOV [Y], BA]]
 
|20
 
|-
 
|CF DD
 
|[[PM_Opc_MOV16|MOV [Y], HL]]
 
|20
 
|-
 
|CF DE
 
|[[PM_Opc_MOV16|MOV [Y], X]]
 
|20
 
|-
 
|CF DF
 
|[[PM_Opc_MOV16|MOV [Y], Y]]
 
|20
 
|-
 
|CF E0
 
|[[PM_Opc_MOV16|MOV BA, BA]]
 
|8
 
|-
 
|CF E1
 
|[[PM_Opc_MOV16|MOV BA, HL]]
 
|8
 
|-
 
|CF E2
 
|[[PM_Opc_MOV16|MOV BA, X]]
 
|8
 
|-
 
|CF E3
 
|[[PM_Opc_MOV16|MOV BA, Y]]
 
|8
 
|-
 
|CF E4
 
|[[PM_Opc_MOV16|MOV HL, BA]]
 
|8
 
|-
 
|CF E5
 
|[[PM_Opc_MOV16|MOV HL, HL]]
 
|8
 
|-
 
|CF E6
 
|[[PM_Opc_MOV16|MOV HL, X]]
 
|8
 
|-
 
|CF E7
 
|[[PM_Opc_MOV16|MOV HL, Y]]
 
|8
 
|-
 
|CF E8
 
|[[PM_Opc_MOV16|MOV X, BA]]
 
|8
 
|-
 
|CF E9
 
|[[PM_Opc_MOV16|MOV X, HL]]
 
|8
 
|-
 
|CF EA
 
|[[PM_Opc_MOV16|MOV X, X]]
 
|8
 
|-
 
|CF EB
 
|[[PM_Opc_MOV16|MOV X, Y]]
 
|8
 
|-
 
|CF EC
 
|[[PM_Opc_MOV16|MOV Y, BA]]
 
|8
 
|-
 
|CF ED
 
|[[PM_Opc_MOV16|MOV Y, HL]]
 
|8
 
|-
 
|CF EE
 
|[[PM_Opc_MOV16|MOV Y, X]]
 
|8
 
|-
 
|CF EF
 
|[[PM_Opc_MOV16|MOV Y, Y]]
 
|8
 
|-
 
|CF F0
 
|[[PM_Opc_MOV16|MOV SP, BA]]
 
|8
 
|-
 
|CF F1
 
|[[PM_Opc_MOV16|MOV SP, HL]]
 
|8
 
|-
 
|CF F2
 
|[[PM_Opc_MOV16|MOV SP, X]]
 
|8
 
|-
 
|CF F3
 
|[[PM_Opc_MOV16|MOV SP, Y]]
 
|8
 
|-
 
|CF F4
 
|[[PM_Opc_MOV16|MOV HL, SP]]
 
|8
 
|-
 
|CF F5
 
|[[PM_Opc_MOV16|MOV HL, PC]]
 
|8
 
|-
 
|CF F8
 
|[[PM_Opc_MOV16|MOV BA, SP]]
 
|8
 
|-
 
|CF F9
 
|[[PM_Opc_MOV16|MOV BA, PC]]
 
|8
 
|-
 
|CF FA
 
|[[PM_Opc_MOV16|MOV X, SP]]
 
|8
 
|-
 
|CF FE
 
|[[PM_Opc_MOV16|MOV Y, SP]]
 
|8
 
|-
 
|}
 
 
 
'''Flags Affected:''' None
 
 
 
= Arithmetic =
 
 
 
== ADD = Addition ==
 
 
 
[[PM_Opc_ADD8|8 Bit Opcode overview]]
 
 
 
[[PM_Opc_ADD16|16 Bit Opcode overview]]
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|00
 
|[[PM_Opc_ADD8|ADD A, A]]
 
|8
 
|-
 
|01
 
|[[PM_Opc_ADD8|ADD A, B]]
 
|8
 
|-
 
|02 nn
 
|[[PM_Opc_ADD8|ADD A, #nn]]
 
|8
 
|-
 
|03
 
|[[PM_Opc_ADD8|ADD A, [HL]]]
 
|8
 
|-
 
|04 nn
 
|[[PM_Opc_ADD8|ADD A, [N+#nn]]]
 
|12
 
|-
 
|05 nn nn
 
|[[PM_Opc_ADD8|ADD A, [#nnnn]]]
 
|16
 
|-
 
|06
 
|[[PM_Opc_ADD8|ADD A, [X]]]
 
|8
 
|-
 
|07
 
|[[PM_Opc_ADD8|ADD A, [Y]]]
 
|8
 
|-
 
|C0 nn nn
 
|[[PM_Opc_ADD16|ADD BA, #nnnn]]
 
|12
 
|-
 
|C1 nn nn
 
|[[PM_Opc_ADD16|ADD HL, #nnnn]]
 
|12
 
|-
 
|C2 nn nn
 
|[[PM_Opc_ADD16|ADD X, #nnnn]]
 
|12
 
|-
 
|C3 nn nn
 
|[[PM_Opc_ADD16|ADD Y, #nnnn]]
 
|12
 
|-
 
|CF 68 nn nn
 
|[[PM_Opc_ADD16|ADD SP, #nnnn]]
 
|16
 
|-
 
|CE 00 ss
 
|[[PM_Opc_ADD8|ADD A, [X+#ss]]]
 
|16
 
|-
 
|CE 01 ss
 
|[[PM_Opc_ADD8|ADD A, [Y+#ss]]]
 
|16
 
|-
 
|CE 02
 
|[[PM_Opc_ADD8|ADD A, [X+L]]]
 
|16
 
|-
 
|CE 03
 
|[[PM_Opc_ADD8|ADD A, [Y+L]]]
 
|16
 
|-
 
|CE 04
 
|[[PM_Opc_ADD8|ADD [HL], A]]
 
|16
 
|-
 
|CE 05 nn
 
|[[PM_Opc_ADD8|ADD [HL], #nn]]
 
|20
 
|-
 
|CE 06
 
|[[PM_Opc_ADD8|ADD [HL], [X]]]
 
|20
 
|-
 
|CE 07
 
|[[PM_Opc_ADD8|ADD [HL], [Y]]]
 
|20
 
|-
 
|CF 00
 
|[[PM_Opc_ADD16|ADD BA, BA]]
 
|16
 
|-
 
|CF 01
 
|[[PM_Opc_ADD16|ADD BA, HL]]
 
|16
 
|-
 
|CF 02
 
|[[PM_Opc_ADD16|ADD BA, X]]
 
|16
 
|-
 
|CF 03
 
|[[PM_Opc_ADD16|ADD BA, Y]]
 
|16
 
|-
 
|CF 20
 
|[[PM_Opc_ADD16|ADD HL, BA]]
 
|16
 
|-
 
|CF 21
 
|[[PM_Opc_ADD16|ADD HL, HL]]
 
|16
 
|-
 
|CF 22
 
|[[PM_Opc_ADD16|ADD HL, X]]
 
|16
 
|-
 
|CF 23
 
|[[PM_Opc_ADD16|ADD HL, Y]]
 
|16
 
|-
 
|CF 40
 
|[[PM_Opc_ADD16|ADD X, BA]]
 
|16
 
|-
 
|CF 41
 
|[[PM_Opc_ADD16|ADD X, HL]]
 
|16
 
|-
 
|CF 42
 
|[[PM_Opc_ADD16|ADD Y, BA]]
 
|16
 
|-
 
|CF 43
 
|[[PM_Opc_ADD16|ADD Y, HL]]
 
|16
 
|-
 
|CF 44
 
|[[PM_Opc_ADD16|ADD SP, BA]]
 
|16
 
|-
 
|CF 45
 
|[[PM_Opc_ADD16|ADD SP, HL]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' All
 
 
 
== SUB = Subtraction ==
 
 
 
[[PM_Opc_SUB8|8 Bit Opcode overview]]
 
 
 
[[PM_Opc_SUB16|16 Bit Opcode overview]]
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|10
 
|[[PM_Opc_SUB8|SUB A, A]]
 
|8
 
|-
 
|11
 
|[[PM_Opc_SUB8|SUB A, B]]
 
|8
 
|-
 
|12 nn
 
|[[PM_Opc_SUB8|SUB A, #nn]]
 
|8
 
|-
 
|13
 
|[[PM_Opc_SUB8|SUB A, [HL]]]
 
|8
 
|-
 
|14 nn
 
|[[PM_Opc_SUB8|SUB A, [N+#nn]]]
 
|12
 
|-
 
|15 nn nn
 
|[[PM_Opc_SUB8|SUB A, [#nnnn]]]
 
|16
 
|-
 
|16
 
|[[PM_Opc_SUB8|SUB A, [X]]]
 
|8
 
|-
 
|17
 
|[[PM_Opc_SUB8|SUB A, [Y]]]
 
|8
 
|-
 
|D0 nn nn
 
|[[PM_Opc_SUB16|SUB BA, #nnnn]]
 
|12
 
|-
 
|D1 nn nn
 
|[[PM_Opc_SUB16|SUB HL, #nnnn]]
 
|12
 
|-
 
|D2 nn nn
 
|[[PM_Opc_SUB16|SUB X, #nnnn]]
 
|12
 
|-
 
|D3 nn nn
 
|[[PM_Opc_SUB16|SUB Y, #nnnn]]
 
|12
 
|-
 
|CF 6A nn nn
 
|[[PM_Opc_SUB16|SUB SP, #nnnn]]
 
|16
 
|-
 
|CE 10 ss
 
|[[PM_Opc_SUB8|SUB A, [X+#ss]]]
 
|16
 
|-
 
|CE 11 ss
 
|[[PM_Opc_SUB8|SUB A, [Y+#ss]]]
 
|16
 
|-
 
|CE 12
 
|[[PM_Opc_SUB8|SUB A, [X+L]]]
 
|16
 
|-
 
|CE 13
 
|[[PM_Opc_SUB8|SUB A, [Y+L]]]
 
|16
 
|-
 
|CE 14
 
|[[PM_Opc_SUB8|SUB [HL], A]]
 
|16
 
|-
 
|CE 15 nn
 
|[[PM_Opc_SUB8|SUB [HL], #nn]]
 
|20
 
|-
 
|CE 16
 
|[[PM_Opc_SUB8|SUB [HL], [X]]]
 
|20
 
|-
 
|CE 17
 
|[[PM_Opc_SUB8|SUB [HL], [Y]]]
 
|20
 
|-
 
|CF 08
 
|[[PM_Opc_SUB16|SUB BA, BA]]
 
|16
 
|-
 
|CF 09
 
|[[PM_Opc_SUB16|SUB BA, HL]]
 
|16
 
|-
 
|CF 0A
 
|[[PM_Opc_SUB16|SUB BA, X]]
 
|16
 
|-
 
|CF 0B
 
|[[PM_Opc_SUB16|SUB BA, Y]]
 
|16
 
|-
 
|CF 28
 
|[[PM_Opc_SUB16|SUB HL, BA]]
 
|16
 
|-
 
|CF 29
 
|[[PM_Opc_SUB16|SUB HL, HL]]
 
|16
 
|-
 
|CF 2A
 
|[[PM_Opc_SUB16|SUB HL, X]]
 
|16
 
|-
 
|CF 2B
 
|[[PM_Opc_SUB16|SUB HL, Y]]
 
|16
 
|-
 
|CF 48
 
|[[PM_Opc_SUB16|SUB X, BA]]
 
|16
 
|-
 
|CF 49
 
|[[PM_Opc_SUB16|SUB X, HL]]
 
|16
 
|-
 
|CF 4A
 
|[[PM_Opc_SUB16|SUB Y, BA]]
 
|16
 
|-
 
|CF 4B
 
|[[PM_Opc_SUB16|SUB Y, HL]]
 
|16
 
|-
 
|CF 4C
 
|[[PM_Opc_SUB16|SUB SP, BA]]
 
|16
 
|-
 
|CF 4D
 
|[[PM_Opc_SUB16|SUB SP, HL]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' All
 
 
 
== ADC = Addition with Carry ==
 
 
 
[[PM_Opc_ADC8|8 Bit Opcode overview]]
 
 
 
[[PM_Opc_ADC16|16 Bit Opcode overview]]
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|08
 
|[[PM_Opc_ADC8|ADC A, A]]
 
|8
 
|-
 
|09
 
|[[PM_Opc_ADC8|ADC A, B]]
 
|8
 
|-
 
|0A nn
 
|[[PM_Opc_ADC8|ADC A, #nn]]
 
|8
 
|-
 
|0B
 
|[[PM_Opc_ADC8|ADC A, [HL]]]
 
|8
 
|-
 
|0C nn
 
|[[PM_Opc_ADC8|ADC A, [N+#nn]]]
 
|12
 
|-
 
|0D nn nn
 
|[[PM_Opc_ADC8|ADC A, [#nnnn]]]
 
|16
 
|-
 
|0E
 
|[[PM_Opc_ADC8|ADC A, [X]]]
 
|8
 
|-
 
|0F
 
|[[PM_Opc_ADC8|ADC A, [Y]]]
 
|8
 
|-
 
|CE 08 ss
 
|[[PM_Opc_ADC8|ADC A, [X+#ss]]]
 
|16
 
|-
 
|CE 09 ss
 
|[[PM_Opc_ADC8|ADC A, [Y+#ss]]]
 
|16
 
|-
 
|CE 0A
 
|[[PM_Opc_ADC8|ADC A, [X+L]]]
 
|16
 
|-
 
|CE 0B
 
|[[PM_Opc_ADC8|ADC A, [Y+L]]]
 
|16
 
|-
 
|CE 0C
 
|[[PM_Opc_ADC8|ADC [HL], A]]
 
|16
 
|-
 
|CE 0D nn
 
|[[PM_Opc_ADC8|ADC [HL], #nn]]
 
|20
 
|-
 
|CE 0E
 
|[[PM_Opc_ADC8|ADC [HL], [X]]]
 
|20
 
|-
 
|CE 0F
 
|[[PM_Opc_ADC8|ADC [HL], [Y]]]
 
|20
 
|-
 
|CF 04
 
|[[PM_Opc_ADC16|ADC BA, BA]]
 
|16
 
|-
 
|CF 05
 
|[[PM_Opc_ADC16|ADC BA, HL]]
 
|16
 
|-
 
|CF 06
 
|[[PM_Opc_ADC16|ADC BA, X]]
 
|16
 
|-
 
|CF 07
 
|[[PM_Opc_ADC16|ADC BA, Y]]
 
|16
 
|-
 
|CF 24
 
|[[PM_Opc_ADC16|ADC HL, BA]]
 
|16
 
|-
 
|CF 25
 
|[[PM_Opc_ADC16|ADC HL, HL]]
 
|16
 
|-
 
|CF 26
 
|[[PM_Opc_ADC16|ADC HL, X]]
 
|16
 
|-
 
|CF 27
 
|[[PM_Opc_ADC16|ADC HL, Y]]
 
|16
 
|-
 
|CF 60 nn nn
 
|[[PM_Opc_ADC16|ADC BA, #nnnn]]
 
|16
 
|-
 
|CF 61 nn nn
 
|[[PM_Opc_ADC16|ADC HL, #nnnn]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' All
 
 
 
== SBC = Subtraction with Carry ==
 
 
 
[[PM_Opc_SBC8|8 Bit Opcode overview]]
 
 
 
[[PM_Opc_SBC16|16 Bit Opcode overview]]
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|18
 
|[[PM_Opc_SBC8|SBC A, A]]
 
|8
 
|-
 
|19
 
|[[PM_Opc_SBC8|SBC A, B]]
 
|8
 
|-
 
|1A nn
 
|[[PM_Opc_SBC8|SBC A, #nn]]
 
|8
 
|-
 
|1B
 
|[[PM_Opc_SBC8|SBC A, [HL]]]
 
|8
 
|-
 
|1C nn
 
|[[PM_Opc_SBC8|SBC A, [N+#nn]]]
 
|12
 
|-
 
|1D nn nn
 
|[[PM_Opc_SBC8|SBC A, [#nnnn]]]
 
|16
 
|-
 
|1E
 
|[[PM_Opc_SBC8|SBC A, [X]]]
 
|8
 
|-
 
|1F
 
|[[PM_Opc_SBC8|SBC A, [Y]]]
 
|8
 
|-
 
|CE 18 ss
 
|[[PM_Opc_SBC8|SBC A, [X+#ss]]]
 
|16
 
|-
 
|CE 19 ss
 
|[[PM_Opc_SBC8|SBC A, [Y+#ss]]]
 
|16
 
|-
 
|CE 1A
 
|[[PM_Opc_SBC8|SBC A, [X+L]]]
 
|16
 
|-
 
|CE 1B
 
|[[PM_Opc_SBC8|SBC A, [Y+L]]]
 
|16
 
|-
 
|CE 1C
 
|[[PM_Opc_SBC8|SBC [HL], A]]
 
|16
 
|-
 
|CE 1D nn
 
|[[PM_Opc_SBC8|SBC [HL], #nn]]
 
|20
 
|-
 
|CE 1E
 
|[[PM_Opc_SBC8|SBC [HL], [X]]]
 
|20
 
|-
 
|CE 1F
 
|[[PM_Opc_SBC8|SBC [HL], [Y]]]
 
|20
 
|-
 
|CF 0C
 
|[[PM_Opc_SBC16|SBC BA, BA]]
 
|16
 
|-
 
|CF 0D
 
|[[PM_Opc_SBC16|SBC BA, HL]]
 
|16
 
|-
 
|CF 0E
 
|[[PM_Opc_SBC16|SBC BA, X]]
 
|16
 
|-
 
|CF 0F
 
|[[PM_Opc_SBC16|SBC BA, Y]]
 
|16
 
|-
 
|CF 2C
 
|[[PM_Opc_SBC16|SBC HL, BA]]
 
|16
 
|-
 
|CF 2D
 
|[[PM_Opc_SBC16|SBC HL, HL]]
 
|16
 
|-
 
|CF 2E
 
|[[PM_Opc_SBC16|SBC HL, X]]
 
|16
 
|-
 
|CF 2F
 
|[[PM_Opc_SBC16|SBC HL, Y]]
 
|16
 
|-
 
|CF 62 nn nn
 
|[[PM_Opc_SBC16|SBC BA, #nnnn]]
 
|16
 
|-
 
|CF 63 nn nn
 
|[[PM_Opc_SBC16|SBC HL, #nnnn]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' All
 
 
 
== CMP = Compare ==
 
 
 
[[PM_Opc_CMP8|8 Bit Opcode overview]]
 
 
 
[[PM_Opc_CMP16|16 Bit Opcode overview]]
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|30
 
|[[PM_Opc_CMP8|CMP A, A]]
 
|8
 
|-
 
|31
 
|[[PM_Opc_CMP8|CMP A, B]]
 
|8
 
|-
 
|32 nn
 
|[[PM_Opc_CMP8|CMP A, #nn]]
 
|8
 
|-
 
|33
 
|[[PM_Opc_CMP8|CMP A, [HL]]]
 
|8
 
|-
 
|34 nn
 
|[[PM_Opc_CMP8|CMP A, [N+#nn]]]
 
|12
 
|-
 
|35 nn nn
 
|[[PM_Opc_CMP8|CMP A, [#nnnn]]]
 
|16
 
|-
 
|36
 
|[[PM_Opc_CMP8|CMP A, [X]]]
 
|8
 
|-
 
|37
 
|[[PM_Opc_CMP8|CMP A, [Y]]]
 
|8
 
|-
 
|D4 nn nn
 
|[[PM_Opc_CMP16|CMP BA, #nnnn]]
 
|12
 
|-
 
|D5 nn nn
 
|[[PM_Opc_CMP16|CMP HL, #nnnn]]
 
|12
 
|-
 
|D6 nn nn
 
|[[PM_Opc_CMP16|CMP X, #nnnn]]
 
|12
 
|-
 
|D7 nn nn
 
|[[PM_Opc_CMP16|CMP Y, #nnnn]]
 
|12
 
|-
 
|CF 6C nn nn
 
|[[PM_Opc_CMP16|CMP SP, #nnnn]]
 
|16
 
|-
 
|DB nn nn
 
|[[PM_Opc_CMP8|CMP [N+#nn], #nn]]
 
|16
 
|-
 
|CE 30 ss
 
|[[PM_Opc_CMP8|CMP A, [X+#ss]]]
 
|16
 
|-
 
|CE 31 ss
 
|[[PM_Opc_CMP8|CMP A, [Y+#ss]]]
 
|16
 
|-
 
|CE 32
 
|[[PM_Opc_CMP8|CMP A, [X+L]]]
 
|16
 
|-
 
|CE 33
 
|[[PM_Opc_CMP8|CMP A, [Y+L]]]
 
|16
 
|-
 
|CE 34
 
|[[PM_Opc_CMP8|CMP [HL], A]]
 
|16
 
|-
 
|CE 35 nn
 
|[[PM_Opc_CMP8|CMP [HL], #nn]]
 
|20
 
|-
 
|CE 36
 
|[[PM_Opc_CMP8|CMP [HL], [X]]]
 
|20
 
|-
 
|CE 37
 
|[[PM_Opc_CMP8|CMP [HL], [Y]]]
 
|20
 
|-
 
|CE BC nn
 
|[[PM_Opc_CMP8|CMP B, #nn]]
 
|12
 
|-
 
|CE BD nn
 
|[[PM_Opc_CMP8|CMP L, #nn]]
 
|12
 
|-
 
|CE BE nn
 
|[[PM_Opc_CMP8|CMP H, #nn]]
 
|12
 
|-
 
|CE BF nn
 
|[[PM_Opc_CMP8|CMP N, #nn]]
 
|12
 
|-
 
|CF 18
 
|[[PM_Opc_CMP16|CMP BA, BA]]
 
|16
 
|-
 
|CF 19
 
|[[PM_Opc_CMP16|CMP BA, HL]]
 
|16
 
|-
 
|CF 1A
 
|[[PM_Opc_CMP16|CMP BA, X]]
 
|16
 
|-
 
|CF 1B
 
|[[PM_Opc_CMP16|CMP BA, Y]]
 
|16
 
|-
 
|CF 38
 
|[[PM_Opc_CMP16|CMP HL, BA]]
 
|16
 
|-
 
|CF 39
 
|[[PM_Opc_CMP16|CMP HL, HL]]
 
|16
 
|-
 
|CF 3A
 
|[[PM_Opc_CMP16|CMP HL, X]]
 
|16
 
|-
 
|CF 3B
 
|[[PM_Opc_CMP16|CMP HL, Y]]
 
|16
 
|-
 
|CF 5C
 
|[[PM_Opc_CMP16|CMP SP, BA]]
 
|16
 
|-
 
|CF 5D
 
|[[PM_Opc_CMP16|CMP SP, HL]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' All
 
 
 
== INC = Increase Register by 1 ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|80
 
|[[PM_Opc_INC|INC A]]
 
|8
 
|-
 
|81
 
|[[PM_Opc_INC|INC B]]
 
|8
 
|-
 
|82
 
|[[PM_Opc_INC|INC L]]
 
|8
 
|-
 
|83
 
|[[PM_Opc_INC|INC H]]
 
|8
 
|-
 
|84
 
|[[PM_Opc_INC|INC N]]
 
|8
 
|-
 
|85 nn
 
|[[PM_Opc_INC|INC [N+#nn]]]
 
|16
 
|-
 
|86
 
|[[PM_Opc_INC|INC [HL]]]
 
|12
 
|-
 
|87
 
|[[PM_Opc_INC|INC SP]]
 
|8
 
|-
 
|90
 
|[[PM_Opc_INC|INC BA]]
 
|8
 
|-
 
|91
 
|[[PM_Opc_INC|INC HL]]
 
|8
 
|-
 
|92
 
|[[PM_Opc_INC|INC X]]
 
|8
 
|-
 
|93
 
|[[PM_Opc_INC|INC Y]]
 
|8
 
|}
 
 
 
'''Flags Affected:''' Zero
 
 
 
== DEC = Decrease Register by 1 ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|88
 
|[[PM_Opc_DEC|DEC A]]
 
|8
 
|-
 
|89
 
|[[PM_Opc_DEC|DEC B]]
 
|8
 
|-
 
|8A
 
|[[PM_Opc_DEC|DEC L]]
 
|8
 
|-
 
|8B
 
|[[PM_Opc_DEC|DEC H]]
 
|8
 
|-
 
|8C
 
|[[PM_Opc_DEC|DEC N]]
 
|8
 
|-
 
|8D nn
 
|[[PM_Opc_DEC|DEC [N+#nn]]]
 
|16
 
|-
 
|8E
 
|[[PM_Opc_DEC|DEC [HL]]]
 
|12
 
|-
 
|8F
 
|[[PM_Opc_DEC|DEC SP]]
 
|8
 
|-
 
|98
 
|[[PM_Opc_DEC|DEC BA]]
 
|8
 
|-
 
|99
 
|[[PM_Opc_DEC|DEC HL]]
 
|8
 
|-
 
|9A
 
|[[PM_Opc_DEC|DEC X]]
 
|8
 
|-
 
|9B
 
|[[PM_Opc_DEC|DEC Y]]
 
|8
 
|}
 
 
 
'''Flags Affected:''' Zero
 
 
 
== NEG = Negate ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE A4
 
|[[PM_Opc_NEG|NEG A]]
 
|12
 
|-
 
|CE A5
 
|[[PM_Opc_NEG|NEG B]]
 
|12
 
|-
 
|CE A6 nn
 
|[[PM_Opc_NEG|NEG [N+#nn]]]
 
|20
 
|-
 
|CE A7
 
|[[PM_Opc_NEG|NEG [HL]]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' All
 
 
 
== MUL = Multiply ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE D8
 
|[[PM_Opc_MUL|MUL L, A]]
 
|48
 
|}
 
 
 
'''Flags Affected:''' All
 
 
 
== DIV = Divide ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE D9
 
|[[PM_Opc_DIV|DIV HL, A]]
 
|52
 
|}
 
 
 
'''Flags Affected:''' All
 
 
 
'''Note:''' Can throw Division by Zero
 
 
 
= Logic =
 
 
 
== TST = Test Bits ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|94
 
|[[PM_Opc_TST|TST A, B]]
 
|8
 
|-
 
|95 nn
 
|[[PM_Opc_TST|TST [HL], #nn]]
 
|12
 
|-
 
|96 nn
 
|[[PM_Opc_TST|TST A, #nn]]
 
|8
 
|-
 
|97 nn
 
|[[PM_Opc_TST|TST B, #nn]]
 
|8
 
|-
 
|DC nn nn
 
|[[PM_Opc_TST|TST [N+#nn], #nn]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' Zero, Sign
 
 
 
== AND = Logical AND ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|20
 
|[[PM_Opc_AND|AND A, A]]
 
|8
 
|-
 
|21
 
|[[PM_Opc_AND|AND A, B]]
 
|8
 
|-
 
|22 nn
 
|[[PM_Opc_AND|AND A, #nn]]
 
|8
 
|-
 
|23
 
|[[PM_Opc_AND|AND A, [HL]]]
 
|8
 
|-
 
|24 nn
 
|[[PM_Opc_AND|AND A, [N+#nn]]]
 
|12
 
|-
 
|25 nn nn
 
|[[PM_Opc_AND|AND A, [#nnnn]]]
 
|16
 
|-
 
|26
 
|[[PM_Opc_AND|AND A, [X]]]
 
|8
 
|-
 
|27
 
|[[PM_Opc_AND|AND A, [Y]]]
 
|8
 
|-
 
|9C nn
 
|[[PM_Opc_AND|AND F, #nn]]
 
|12
 
|-
 
|CE B0 nn
 
|[[PM_Opc_AND|AND B, #nn]]
 
|12
 
|-
 
|CE B1 nn
 
|[[PM_Opc_AND|AND L, #nn]]
 
|12
 
|-
 
|CE B2 nn
 
|[[PM_Opc_AND|AND H, #nn]]
 
|12
 
|-
 
|D8 nn nn
 
|[[PM_Opc_AND|AND [N+#nn], #nn]]
 
|20
 
|-
 
|CE 20 ss
 
|[[PM_Opc_AND|AND A, [X+#ss]]]
 
|16
 
|-
 
|CE 21 ss
 
|[[PM_Opc_AND|AND A, [Y+#ss]]]
 
|16
 
|-
 
|CE 22
 
|[[PM_Opc_AND|AND A, [X+L]]]
 
|16
 
|-
 
|CE 23
 
|[[PM_Opc_AND|AND A, [Y+L]]]
 
|16
 
|-
 
|CE 24
 
|[[PM_Opc_AND|AND [HL], A]]
 
|16
 
|-
 
|CE 25 nn
 
|[[PM_Opc_AND|AND [HL], #nn]]
 
|20
 
|-
 
|CE 26
 
|[[PM_Opc_AND|AND [HL], [X]]]
 
|20
 
|-
 
|CE 27
 
|[[PM_Opc_AND|AND [HL], [Y]]]
 
|20
 
|}
 
 
 
'''Flags Affected:''' Zero, Sign
 
 
 
== OR = Logical Inclusive-OR ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|28
 
|[[PM_Opc_OR|OR A, A]]
 
|8
 
|-
 
|29
 
|[[PM_Opc_OR|OR A, B]]
 
|8
 
|-
 
|2A nn
 
|[[PM_Opc_OR|OR A, #nn]]
 
|8
 
|-
 
|2B
 
|[[PM_Opc_OR|OR A, [HL]]]
 
|8
 
|-
 
|2C nn
 
|[[PM_Opc_OR|OR A, [N+#nn]]]
 
|12
 
|-
 
|2D nn nn
 
|[[PM_Opc_OR|OR A, [#nnnn]]]
 
|16
 
|-
 
|2E
 
|[[PM_Opc_OR|OR A, [X]]]
 
|8
 
|-
 
|2F
 
|[[PM_Opc_OR|OR A, [Y]]]
 
|8
 
|-
 
|9D nn
 
|[[PM_Opc_OR|OR F, #nn]]
 
|12
 
|-
 
|CE B4 nn
 
|[[PM_Opc_OR|OR B, #nn]]
 
|12
 
|-
 
|CE B5 nn
 
|[[PM_Opc_OR|OR L, #nn]]
 
|12
 
|-
 
|CE B6 nn
 
|[[PM_Opc_OR|OR H, #nn]]
 
|12
 
|-
 
|D9 nn nn
 
|[[PM_Opc_OR|OR [N+#nn], #nn]]
 
|20
 
|-
 
|CE 28 ss
 
|[[PM_Opc_OR|OR A, [X+#ss]]]
 
|16
 
|-
 
|CE 29 ss
 
|[[PM_Opc_OR|OR A, [Y+#ss]]]
 
|16
 
|-
 
|CE 2A
 
|[[PM_Opc_OR|OR A, [X+L]]]
 
|16
 
|-
 
|CE 2B
 
|[[PM_Opc_OR|OR A, [Y+L]]]
 
|16
 
|-
 
|CE 2C
 
|[[PM_Opc_OR|OR [HL], A]]
 
|16
 
|-
 
|CE 2D nn
 
|[[PM_Opc_OR|OR [HL], #nn]]
 
|20
 
|-
 
|CE 2E
 
|[[PM_Opc_OR|OR [HL], [X]]]
 
|20
 
|-
 
|CE 2F
 
|[[PM_Opc_OR|OR [HL], [Y]]]
 
|20
 
|}
 
 
 
'''Flags Affected:''' Zero, Sign
 
 
 
== XOR = Logical Exclusive-OR ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|38
 
|[[PM_Opc_XOR|XOR A, A]]
 
|8
 
|-
 
|39
 
|[[PM_Opc_XOR|XOR A, B]]
 
|8
 
|-
 
|3A nn
 
|[[PM_Opc_XOR|XOR A, #nn]]
 
|8
 
|-
 
|3B
 
|[[PM_Opc_XOR|XOR A, [HL]]]
 
|8
 
|-
 
|3C nn
 
|[[PM_Opc_XOR|XOR A, [N+#nn]]]
 
|12
 
|-
 
|3D nn nn
 
|[[PM_Opc_XOR|XOR A, [#nnnn]]]
 
|16
 
|-
 
|3E
 
|[[PM_Opc_XOR|XOR A, [X]]]
 
|8
 
|-
 
|3F
 
|[[PM_Opc_XOR|XOR A, [Y]]]
 
|8
 
|-
 
|9E nn
 
|[[PM_Opc_XOR|XOR F, #nn]]
 
|12
 
|-
 
|CE B8 nn
 
|[[PM_Opc_XOR|XOR B, #nn]]
 
|12
 
|-
 
|CE B9 nn
 
|[[PM_Opc_XOR|XOR L, #nn]]
 
|12
 
|-
 
|CE BA nn
 
|[[PM_Opc_XOR|XOR H, #nn]]
 
|12
 
|-
 
|DA nn nn
 
|[[PM_Opc_XOR|XOR [N+#nn], #nn]]
 
|20
 
|-
 
|CE 38 ss
 
|[[PM_Opc_XOR|XOR A, [X+#ss]]]
 
|16
 
|-
 
|CE 39 ss
 
|[[PM_Opc_XOR|XOR A, [Y+#ss]]]
 
|16
 
|-
 
|CE 3A
 
|[[PM_Opc_XOR|XOR A, [X+L]]]
 
|16
 
|-
 
|CE 3B
 
|[[PM_Opc_XOR|XOR A, [Y+L]]]
 
|16
 
|-
 
|CE 3C
 
|[[PM_Opc_XOR|XOR [HL], A]]
 
|16
 
|-
 
|CE 3D nn
 
|[[PM_Opc_XOR|XOR [HL], #nn]]
 
|20
 
|-
 
|CE 3E
 
|[[PM_Opc_XOR|XOR [HL], [X]]]
 
|20
 
|-
 
|CE 3F
 
|[[PM_Opc_XOR|XOR [HL], [Y]]]
 
|20
 
|}
 
 
 
'''Flags Affected:''' Zero, Sign
 
 
 
== NOT = Logical NOT ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE A0
 
|[[PM_Opc_NOT|NOT A]]
 
|12
 
|-
 
|CE A1
 
|[[PM_Opc_NOT|NOT B]]
 
|12
 
|-
 
|CE A2 nn
 
|[[PM_Opc_NOT|NOT [N+#nn]]]
 
|20
 
|-
 
|CE A3
 
|[[PM_Opc_NOT|NOT [HL]]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' Zero, Sign
 
 
 
= Shift & Rotate =
 
 
 
== SHL = Shift Left ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE 84
 
|[[PM_Opc_SHL|SHL A]]
 
|12
 
|-
 
|CE 85
 
|[[PM_Opc_SHL|SHL B]]
 
|12
 
|-
 
|CE 86 nn
 
|[[PM_Opc_SHL|SHL [N+#nn]]]
 
|20
 
|-
 
|CE 87
 
|[[PM_Opc_SHL|SHL [HL]]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' Zero, Carry, Sign
 
 
 
== SAL = Shift Arithmetic Left ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE 80
 
|[[PM_Opc_SAL|SAL A]]
 
|12
 
|-
 
|CE 81
 
|[[PM_Opc_SAL|SAL B]]
 
|12
 
|-
 
|CE 82 nn
 
|[[PM_Opc_SAL|SAL [N+#nn]]]
 
|20
 
|-
 
|CE 83
 
|[[PM_Opc_SAL|SAL [HL]]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' All
 
 
 
== SHR = Shift Right ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE 8C
 
|[[PM_Opc_SHR|SHR A]]
 
|12
 
|-
 
|CE 8D
 
|[[PM_Opc_SHR|SHR B]]
 
|12
 
|-
 
|CE 8E nn
 
|[[PM_Opc_SHR|SHR [N+#nn]]]
 
|20
 
|-
 
|CE 8F
 
|[[PM_Opc_SHR|SHR [HL]]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' Zero, Carry, Sign
 
 
 
== SAR = Shift Arithmetic Right ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE 88
 
|[[PM_Opc_SAR|SAR A]]
 
|12
 
|-
 
|CE 89
 
|[[PM_Opc_SAR|SAR B]]
 
|12
 
|-
 
|CE 8A nn
 
|[[PM_Opc_SAR|SAR [N+#nn]]]
 
|20
 
|-
 
|CE 8B
 
|[[PM_Opc_SAR|SAR [HL]]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' All
 
 
 
== ROL = Rotate Left ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE 94
 
|[[PM_Opc_ROL|ROL A]]
 
|12
 
|-
 
|CE 95
 
|[[PM_Opc_ROL|ROL B]]
 
|12
 
|-
 
|CE 96 nn
 
|[[PM_Opc_ROL|ROL [N+#nn]]]
 
|20
 
|-
 
|CE 97
 
|[[PM_Opc_ROL|ROL [HL]]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' Zero, Carry, Sign
 
 
 
== ROLC = Rotate Left through Carry ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE 90
 
|[[PM_Opc_ROLC|ROLC A]]
 
|12
 
|-
 
|CE 91
 
|[[PM_Opc_ROLC|ROLC B]]
 
|12
 
|-
 
|CE 92 nn
 
|[[PM_Opc_ROLC|ROLC [N+#nn]]]
 
|20
 
|-
 
|CE 93
 
|[[PM_Opc_ROLC|ROLC [HL]]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' Zero, Carry, Sign
 
 
 
== ROR = Rotate Right ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE 9C
 
|[[PM_Opc_ROR|ROR A]]
 
|12
 
|-
 
|CE 9D
 
|[[PM_Opc_ROR|ROR B]]
 
|12
 
|-
 
|CE 9E nn
 
|[[PM_Opc_ROR|ROR [N+#nn]]]
 
|20
 
|-
 
|CE 9F
 
|[[PM_Opc_ROR|ROR [HL]]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' Zero, Carry, Sign
 
 
 
== RORC = Rotate Right through Carry ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE 98
 
|[[PM_Opc_RORC|RORC A]]
 
|12
 
|-
 
|CE 99
 
|[[PM_Opc_RORC|RORC B]]
 
|12
 
|-
 
|CE 9A nn
 
|[[PM_Opc_RORC|RORC [N+#nn]]]
 
|20
 
|-
 
|CE 9B
 
|[[PM_Opc_RORC|RORC [HL]]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' Zero, Carry, Sign
 
 
 
= Swap & Expand =
 
 
 
== XCHG = Exchange Registers ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|C8
 
|[[PM_Opc_XCHG|XCHG BA, HL]]
 
|12
 
|-
 
|C9
 
|[[PM_Opc_XCHG|XCHG BA, X]]
 
|12
 
|-
 
|CA
 
|[[PM_Opc_XCHG|XCHG BA, Y]]
 
|12
 
|-
 
|CB
 
|[[PM_Opc_XCHG|XCHG BA, SP]]
 
|12
 
|-
 
|CC
 
|[[PM_Opc_XCHG|XCHG A, B]]
 
|8
 
|-
 
|CD
 
|[[PM_Opc_XCHG|XCHG A, [HL]]]
 
|12
 
|}
 
 
 
'''Flags Affected:''' None
 
 
 
== PACK / UNPACK = Pack and Unpack Nibbles ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|DE
 
|[[PM_Opc_PACK|PACK]]
 
|8
 
|-
 
|DF
 
|[[PM_Opc_UNPACK|UNPACK]]
 
|8
 
|}
 
 
 
'''Flags Affected:''' None
 
 
 
== SWAP = Swap Low and High Nibbles ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|F6
 
|[[PM_Opc_SWAP|SWAP A]]
 
|8
 
|-
 
|F7
 
|[[PM_Opc_SWAP|SWAP [HL]]]
 
|12
 
|}
 
 
 
'''Flags Affected:''' None
 
 
 
== EX = Expand Register ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE A8
 
|[[PM_Opc_EX|EX BA, A]]
 
|12
 
|}
 
 
 
'''Flags Affected:''' None
 
 
 
= Stack =
 
 
 
== PUSH = Push Register into Stack ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
!Regs stacked from top to bottom
 
|-
 
|A0
 
|[[PM_Opc_PUSH|PUSH BA]]
 
|16
 
|B, A
 
|-
 
|A1
 
|[[PM_Opc_PUSH|PUSH HL]]
 
|16
 
|H, L
 
|-
 
|A2
 
|[[PM_Opc_PUSH|PUSH X]]
 
|16
 
|X(Hi), X(Lo)
 
|-
 
|A3
 
|[[PM_Opc_PUSH|PUSH Y]]
 
|16
 
|Y(Hi), Y(Lo)
 
|-
 
|A4
 
|[[PM_Opc_PUSH|PUSH N]]
 
|12
 
|N
 
|-
 
|A5
 
|[[PM_Opc_PUSH|PUSH I]]
 
|12
 
|I
 
|-
 
|A6
 
|[[PM_Opc_PUSH|PUSHX]]
 
|16
 
|XI, YI
 
|-
 
|A7
 
|[[PM_Opc_PUSH|PUSH F]]
 
|12
 
|F
 
|-
 
|CF B0
 
|[[PM_Opc_PUSH|PUSH A]]
 
|12
 
|A
 
|-
 
|CF B1
 
|[[PM_Opc_PUSH|PUSH B]]
 
|12
 
|B
 
|-
 
|CF B2
 
|[[PM_Opc_PUSH|PUSH L]]
 
|12
 
|L
 
|-
 
|CF B3
 
|[[PM_Opc_PUSH|PUSH H]]
 
|12
 
|H
 
|-
 
|CF B8
 
|[[PM_Opc_PUSH|PUSHA]]
 
|48
 
|B, A, H, L, X(Hi:Lo), Y(Hi:Lo), N
 
|-
 
|CF B9
 
|[[PM_Opc_PUSH|PUSHAX]]
 
|60
 
|B, A, H, L, X(Hi:Lo), Y(Hi:Lo), N, I, XI, YI
 
|}
 
 
 
'''Flags Affected:''' None
 
 
 
== POP = Pop Register from Stack ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
!Regs stacked from top to bottom
 
|-
 
|A8
 
|[[PM_Opc_POP|POP BA]]
 
|12
 
|B, A
 
|-
 
|A9
 
|[[PM_Opc_POP|POP HL]]
 
|12
 
|H, L
 
|-
 
|AA
 
|[[PM_Opc_POP|POP X]]
 
|12
 
|X(Hi), X(Lo)
 
|-
 
|AB
 
|[[PM_Opc_POP|POP Y]]
 
|12
 
|Y(Hi), Y(Lo)
 
|-
 
|AC
 
|[[PM_Opc_POP|POP N]]
 
|8
 
|N
 
|-
 
|AD
 
|[[PM_Opc_POP|POP I]]
 
|8
 
|I
 
|-
 
|AE
 
|[[PM_Opc_POP|POPX]]
 
|12
 
|XI, YI
 
|-
 
|AF
 
|[[PM_Opc_POP|POP F]]
 
|8
 
|F
 
|-
 
|CF B4
 
|[[PM_Opc_POP|POP A]]
 
|12
 
|A
 
|-
 
|CF B5
 
|[[PM_Opc_POP|POP B]]
 
|12
 
|B
 
|-
 
|CF B6
 
|[[PM_Opc_POP|POP L]]
 
|12
 
|L
 
|-
 
|CF B7
 
|[[PM_Opc_POP|POP H]]
 
|12
 
|H
 
|-
 
|CF BC
 
|[[PM_Opc_POP|POPA]]
 
|44
 
|B, A, H, L, X(Hi:Lo), Y(Hi:Lo), N
 
|-
 
|CF BD
 
|[[PM_Opc_POP|POPAX]]
 
|56
 
|B, A, H, L, X(Hi:Lo), Y(Hi:Lo), N, I, XI, YI
 
|}
 
 
 
'''Flags Affected:''' None
 
  
 
= Branch =
 
= Branch =
 +
== ''JRS'' Relative short jump ==
 +
== ''JRL'' Relative long jump ==
 +
== ''JP'' Indirect jump ==
 +
== ''DJR'' Loop ==
 +
== ''CARS'' Relative short call ==
 +
== ''CARL'' Relative long call ==
 +
== ''CALL'' Indirect call ==
 +
== ''RET'' Return ==
 +
== ''RETE'' Exception processing return ==
 +
== ''RETS'' Return and skip ==
 +
== ''INT'' Software interrupt ==
  
== CALL = Call routine ==
+
= System Control =
 +
== ''NOP'' No operation ==
 +
== ''HALT'' Shifts to HALT status ==
 +
== ''SLP'' Shifts to SLEEP status ==
  
{| border="1" style="text-align:left" class="sortable"
+
= Illegal Instructions =
!Hex
 
!Mnemonic
 
!Cycles,True
 
!or False
 
!Condition
 
|-
 
|E0 ss
 
|[[PM_Opc_CALL|CALLCB #ss]]<SUP>*1</SUP>
 
|20
 
|8
 
|Carry=1
 
|-
 
|E1 ss
 
|[[PM_Opc_CALL|CALLNCB #ss]]<SUP>*1</SUP>
 
|20
 
|8
 
|Carry=0
 
|-
 
|E2 ss
 
|[[PM_Opc_CALL|CALLZB #ss]]<SUP>*1</SUP>
 
|20
 
|8
 
|Zero=1
 
|-
 
|E3 ss
 
|[[PM_Opc_CALL|CALLNZB #ss]]<SUP>*1</SUP>
 
|20
 
|8
 
|Zero=0
 
|-
 
|E8 ss ss
 
|[[PM_Opc_CALL|CALLCW #ssss]]<SUP>*1</SUP>
 
|24
 
|12
 
|Carry=1
 
|-
 
|E9 ss ss
 
|[[PM_Opc_CALL|CALLNCW #ssss]]<SUP>*1</SUP>
 
|24
 
|12
 
|Carry=0
 
|-
 
|EA ss ss
 
|[[PM_Opc_CALL|CALLZW #ssss]]<SUP>*1</SUP>
 
|24
 
|12
 
|Zero=1
 
|-
 
|EB ss ss
 
|[[PM_Opc_CALL|CALLNZW #ssss]]<SUP>*1</SUP>
 
|24
 
|12
 
|Zero=0
 
|-
 
|F0 ss
 
|[[PM_Opc_CALL|CALLB #ss]]<SUP>*1</SUP>
 
|20
 
|None
 
|None
 
|-
 
|F2 ss ss
 
|[[PM_Opc_CALL|CALLW #ssss]]<SUP>*1</SUP>
 
|24
 
|None
 
|None
 
|-
 
|FB nn nn
 
|[[PM_Opc_CALL|CALL [#nnnn]]]
 
|20
 
|None
 
|None
 
|-
 
|FC ss
 
|[[PM_Opc_CALL|CINT #nn]]
 
|20
 
|None
 
|None
 
|-
 
|CE F0 ss
 
|[[PM_Opc_CALL|CALLL #ss]]
 
|24
 
|12
 
|(Overflow=1) != (Sign=1)
 
|-
 
|CE F1 ss
 
|[[PM_Opc_CALL|CALLLE #ss]]
 
|24
 
|12
 
|((Overflow=0) != (Sign=0)) OR (Zero=1)
 
|-
 
|CE F2 ss
 
|[[PM_Opc_CALL|CALLG #ss]]
 
|24
 
|12
 
|((Overflow=1) == (Sign=1)) AND (Zero=0)
 
|-
 
|CE F3 ss
 
|[[PM_Opc_CALL|CALLGE #ss]]
 
|24
 
|12
 
|(Overflow=0) == (Sign=0)
 
|-
 
|CE F4 ss
 
|[[PM_Opc_CALL|CALLO #ss]]
 
|24
 
|12
 
|Overflow=1
 
|-
 
|CE F5 ss
 
|[[PM_Opc_CALL|CALLNO #ss]]
 
|24
 
|12
 
|Overflow=0
 
|-
 
|CE F6 ss
 
|[[PM_Opc_CALL|CALLNS #ss]]
 
|24
 
|12
 
|Sign=0
 
|-
 
|CE F7 ss
 
|[[PM_Opc_CALL|CALLS #ss]]
 
|24
 
|12
 
|Sign=1
 
|-
 
|CE F8 ss
 
|[[PM_Opc_CALL|CALLNX0 #ss]]
 
|24
 
|12
 
|??
 
|-
 
|CE F9 ss
 
|[[PM_Opc_CALL|CALLNX1 #ss]]
 
|24
 
|12
 
|??
 
|-
 
|CE FA ss
 
|[[PM_Opc_CALL|CALLNX2 #ss]]
 
|24
 
|12
 
|??
 
|-
 
|CE FB ss
 
|[[PM_Opc_CALL|CALLNX3 #ss]]
 
|24
 
|12
 
|??
 
|-
 
|CE FC ss
 
|[[PM_Opc_CALL|CALLX0 #ss]]
 
|24
 
|12
 
|??
 
|-
 
|CE FD ss
 
|[[PM_Opc_CALL|CALLX1 #ss]]
 
|24
 
|12
 
|??
 
|-
 
|CE FE ss
 
|[[PM_Opc_CALL|CALLX2 #ss]]
 
|24
 
|12
 
|??
 
|-
 
|CE FF ss
 
|[[PM_Opc_CALL|CALLX3 #ss]]
 
|24
 
|12
 
|??
 
|}
 
 
 
'''*1''': CALL, CALLC, CALLNC, CALLZ and CALLNZ can be used in the assembler to auto-detect the appropriate range.
 
 
 
'''Flags Affected:''' None
 
  
== JMP = Jump to routine ==
+
''NOTE: This document is now out of date, as should be updated to the new mnemonic and register naming''
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
!Condition
 
|-
 
|E4 ss
 
|[[PM_Opc_JMP|JCB #ss]]<SUP>*1</SUP>
 
|8
 
|Carry=1
 
|-
 
|E5 ss
 
|[[PM_Opc_JMP|JNCB #ss]]<SUP>*1</SUP>
 
|8
 
|Carry=0
 
|-
 
|E6 ss
 
|[[PM_Opc_JMP|JZB #ss]]<SUP>*1</SUP>
 
|8
 
|Zero=1
 
|-
 
|E7 ss
 
|[[PM_Opc_JMP|JNZB #ss]]<SUP>*1</SUP>
 
|8
 
|Zero=0
 
|-
 
|EC ss ss
 
|[[PM_Opc_JMP|JCW #ssss]]<SUP>*1</SUP>
 
|12
 
|Carry=1
 
|-
 
|ED ss ss
 
|[[PM_Opc_JMP|JNCW #ssss]]<SUP>*1</SUP>
 
|12
 
|Carry=0
 
|-
 
|EE ss ss
 
|[[PM_Opc_JMP|JZW #ssss]]<SUP>*1</SUP>
 
|12
 
|Zero=1
 
|-
 
|EF ss ss
 
|[[PM_Opc_JMP|JNZW #ssss]]<SUP>*1</SUP>
 
|12
 
|Zero=0
 
|-
 
|F1 ss
 
|[[PM_Opc_JMP|JMPB #ss]]<SUP>*1</SUP>
 
|8
 
|None
 
|-
 
|F3 ss ss
 
|[[PM_Opc_JMP|JMPW #ssss]]<SUP>*1</SUP>
 
|12
 
|None
 
|-
 
|F4
 
|[[PM_Opc_JMP|JMP HL]]
 
|8
 
|None
 
|-
 
|F5 ss
 
|[[PM_Opc_JMP|JDBNZ #ss]]
 
|16
 
|B <> 0x00, decrement B before check
 
|-
 
|FD nn
 
|[[PM_Opc_JMP|JINT #nn]]
 
|8
 
|None
 
|-
 
|CE E0 ss
 
|[[PM_Opc_JMP|JL #ss]]
 
|12
 
|(Overflow=1) != (Sign=1)
 
|-
 
|CE E1 ss
 
|[[PM_Opc_JMP|JLE #ss]]
 
|12
 
|((Overflow=0) != (Sign=0)) OR (Zero=1)
 
|-
 
|CE E2 ss
 
|[[PM_Opc_JMP|JG #ss]]
 
|12
 
|((Overflow=1) == (Sign=1)) AND (Zero=0)
 
|-
 
|CE E3 ss
 
|[[PM_Opc_JMP|JGE #ss]]
 
|12
 
|(Overflow=0) == (Sign=0)
 
|-
 
|CE E4 ss
 
|[[PM_Opc_JMP|JO #ss]]
 
|12
 
|Overflow=1
 
|-
 
|CE E5 ss
 
|[[PM_Opc_JMP|JNO #ss]]
 
|12
 
|Overflow=0
 
|-
 
|CE E6 ss
 
|[[PM_Opc_JMP|JNS #ss]]
 
|12
 
|Sign=0
 
|-
 
|CE E7 ss
 
|[[PM_Opc_JMP|JS #ss]]
 
|12
 
|Sign=1
 
|-
 
|CE E8 ss
 
|[[PM_Opc_JMP|JNX0 #ss]]
 
|12
 
|??
 
|-
 
|CE E9 ss
 
|[[PM_Opc_JMP|JNX1 #ss]]
 
|12
 
|??
 
|-
 
|CE EA ss
 
|[[PM_Opc_JMP|JNX2 #ss]]
 
|12
 
|??
 
|-
 
|CE EB ss
 
|[[PM_Opc_JMP|JNX3 #ss]]
 
|12
 
|??
 
|-
 
|CE EC ss
 
|[[PM_Opc_JMP|JX0 #ss]]
 
|12
 
|??
 
|-
 
|CE ED ss
 
|[[PM_Opc_JMP|JX1 #ss]]
 
|12
 
|??
 
|-
 
|CE EE ss
 
|[[PM_Opc_JMP|JX2 #ss]]
 
|12
 
|??
 
|-
 
|CE EF ss
 
|[[PM_Opc_JMP|JX3 #ss]]
 
|12
 
|??
 
|}
 
 
 
'''*1''': JMP, JC, JNC, JZ and JNZ can be used in the assembler to auto-detect the appropriate range.
 
 
 
'''Flags Affected (0xF5 - JDBNZ #ss):''' Zero
 
 
 
'''Flags Affected (Others):''' None
 
 
 
== RET = Return from routine ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|F8
 
|[[PM_Opc_RET|RET]]
 
|16
 
|-
 
|F9
 
|[[PM_Opc_RET|RETI]]
 
|16
 
|-
 
|FA
 
|[[PM_Opc_RET|RETSKIP]]
 
|16
 
|}
 
 
 
'''Flags Affected:''' None
 
 
 
= System =
 
 
 
== HALT = Halt CPU ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE AE
 
|[[PM_Opc_HALT|HALT]]
 
|8
 
|}
 
 
 
'''Flags Affected:''' None
 
 
 
== STOP = Stop CPU ==
 
 
 
{| border="1" style="text-align:left" class="sortable"
 
!Hex
 
!Mnemonic
 
!Cycles
 
|-
 
|CE AF
 
|[[PM_Opc_STOP|STOP]]
 
|8
 
|}
 
 
 
'''Flags Affected:''' None
 
 
 
= Illegal Instructions =
 
  
 
The entire opcode table has been evaluated on Pokemon Mini units and new and exotic illegal opcodes have been found.
 
The entire opcode table has been evaluated on Pokemon Mini units and new and exotic illegal opcodes have been found.

Revision as of 00:28, 11 July 2015

8-bit arithmetic and logic operation

ADD Addition

ADC Addition with carry

SUB Subtraction

SBC Subtraction with carry

AND Logical product

OR Logical sum

XOR Exclusive OR

CP Comparison

BIT Bit test

INC 1 increment

DEC 1 decrement

MLT Multiplication

DIV Division

CPL Complement of 1

NEG Complement of 2

8-bit transfer

LD Load

EX Byte exchange

SWAP Nibble exchange

Rotate/shift

RL Rotate to left

RLC Rotate to left with carry

RR Rotate to right

RRC Rotate to right with carry

SLA Arithmetic shift to left

SLL Logical shift to left

SRA Arithmetic shift to right

SRL Logical shift to right

Auxiliary operation

PACK Pack

UPCK Unpack

SEP Code extension

16-bit arithmetic operation

ADD Addition

ADC Addition with carry

SUB Subtraction

SBC Subtraction with carry

CP Comparison

INC 1 increment

DEC 1 decrement

16-bit transfer

LD Load

EX Word exchange

Stack Control

PUSH Push

POP Pop

Branch

JRS Relative short jump

JRL Relative long jump

JP Indirect jump

DJR Loop

CARS Relative short call

CARL Relative long call

CALL Indirect call

RET Return

RETE Exception processing return

RETS Return and skip

INT Software interrupt

System Control

NOP No operation

HALT Shifts to HALT status

SLP Shifts to SLEEP status

Illegal Instructions

NOTE: This document is now out of date, as should be updated to the new mnemonic and register naming

The entire opcode table has been evaluated on Pokemon Mini units and new and exotic illegal opcodes have been found.

These opcodes are not officially supported (they are not used by commercial games and not even found in the Pokemon Channel emulator) and can produce random results or crashes in some cases. The illegal opcodes have been documented on this page's Discussion page.