Timers
Timer Overview
The Pokemon Mini overs 3 general purpose timer units. Each timer is broken down into several blocks to provide it with variable clock rates, the ability to be broken down into two independent 8-bit timers, and each timer can generate two unique interrupts.
Timer Control
Each timer is configured using 4 registers, TIM_SCALE*, TIM_SPEED*, TIM_CTL*_L and TIM_CTL*_H. These registers provide the ability to change the clock rate of both the low and high 8-bits of the counter, set if there is a barrow chain to the upper 8-bits (16-bit counter mode) as well as enable and reset the timer. Beginning with the TIM_SPEED*, each timer has the ability to run in either SLOW or FAST mode. Depending on this mode, the timer's pre-scale clock divider is determined. Both 8-bit values can have their own pre-scale value. The pre-scale is further decided by selecting one of 8 different pre-scale values from a table in the TIM_SCALE* register.
Futher more, timers must be enabled individually (by setting the enable flag in TIM_SCALE* TIM_CTL*_L and TIM_CTL*_H) as well as by group (Upper half of TIM_SPEED1_ENA). TIM_SPEED1_ENA disables all slow or all fast timers if either respective bit is clear ($10 and $20).
| Fast | Slow | |
|---|---|---|
| 0 | /2 | /128 |
| 1 | /8 | /256 |
| 2 | /32 | /512 |
| 3 | /64 | /1024 |
| 4 | /128 | /2048 |
| 5 | /256 | /4096 |
| 6 | /1024 | /8192 |
| 7 | /4096 | /16384 |
The timer control registers affect the values of the timers themselves. Enable must be set for timing, this means there are a total of 3 bits that must be enabled for any timer to begin counting. writing a logical 1 to a reset bit in a control register will cause that respective 8-bit section to copy the respective value out of preset. All timers count down. When any timer underflows, it's value is copied from the preset value.
16-bit mode
When a timer is operating in 16-bit mode, all the upper-8 bit settings are unceremoniously ignored. Enables, reset and and everything else simply because data blackholes, they are writable, but they no longer actively function. This includes enables, resets and pre-scale values. The lower-8 bit configuration is effective over the full 16-bit value. Additionally, all lower-8 underflow IRQs are effectively disabled. The timer only presets when the full 16-bit value underflows.
IRQ Operation
Each timer provides two irqs. These IRQs appear to be fixed function, which provides the only known difference between Timers 1-2 and Timer 3.
Timers 1-3 have a primary IRQ, this fires anytime the upper 8-bit of the counter underflows (16- or 8-bit operations) The secondary IRQ of Timer 1-2 occurs when the lower 8-bit counter underflows (8-bit mode only) The secondary IRQ of Timer 3 occurs when the value of the counter becomes less than or equal-to the value in it's comparator. In 8-bit mode only the upper 8-bit of the value is used.
